3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 long int initdram (int board_type)
31 /* configure SDRAM start/end */
32 #if defined(CONFIG_MPC5200)
33 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x00000018;/* 32M at 0x0 */
34 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x02000000;/* disabled */
36 /* setup config registers */
37 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2233a00;
38 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
40 /* unlock mode register */
41 *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0000;
42 /* precharge all banks */
43 *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002;
44 /* set mode register */
45 *(vu_long *)MPC5XXX_SDRAM_MODE = 0x408d0000;
46 /* precharge all banks */
47 *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002;
49 *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004;
50 /* set mode register */
51 *(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
52 /* normal operation */
53 *(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000;
54 #elif defined(CONFIG_MGT5100)
55 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
56 *(vu_long *)MPC5XXX_SDRAM_STOP = 0x000007ff;/* 64M */
57 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
59 /* setup config registers */
60 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2222600;
61 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
63 /* address select register */
64 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = 0x03000000;
66 /* unlock mode register */
67 *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0000;
68 /* precharge all banks */
69 *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0002;
70 /* set mode register */
71 *(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
72 /* precharge all banks */
73 *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0002;
75 *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0004;
76 /* set mode register */
77 *(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
78 /* normal operation */
79 *(vu_long *)MPC5XXX_SDRAM_CTRL = 0x514f0000;
83 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
86 /* return total ram size */
87 #if defined(CONFIG_MGT5100)
88 return (64 * 1024 * 1024);
89 #elif defined(CONFIG_MPC5200)
90 return (32 * 1024 * 1024);
96 #if defined(CONFIG_MPC5200)
97 puts ("Board: Motorola MPC5200 (IceCube)\n");
98 #elif defined(CONFIG_MGT5100)
99 puts ("Board: Motorola MGT5100 (IceCube)\n");
104 void flash_preinit(void)
107 * Now, when we are in RAM, enable flash write
108 * access for detection process.
109 * Note that CS_BOOT cannot be cleared when
110 * executing in flash.
112 #if defined(CONFIG_MGT5100)
113 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
114 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
116 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
120 static struct pci_controller hose;
122 extern void pci_mpc5xxx_init(struct pci_controller *);
124 void pci_init_board(void)
126 pci_mpc5xxx_init(&hose);