1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2019 Linaro
4 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12 #include <asm/arch/hi3660.h>
13 #include <asm/armv8/mmu.h>
15 #include <linux/arm-smccc.h>
16 #include <linux/psci.h>
18 #define PMIC_REG_TO_BUS_ADDR(x) (x << 2)
19 #define PMIC_VSEL_MASK 0x7
21 DECLARE_GLOBAL_DATA_PTR;
23 #if !CONFIG_IS_ENABLED(OF_CONTROL)
24 #include <dm/platform_data/serial_pl01x.h>
26 static const struct pl01x_serial_platdata serial_platdata = {
27 .base = HI3660_UART6_BASE,
32 U_BOOT_DEVICE(hikey960_serial0) = {
33 .name = "serial_pl01x",
34 .platdata = &serial_platdata,
38 static struct mm_region hikey_mem_map[] = {
40 .virt = 0x0UL, /* DDR */
43 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
46 .virt = 0xE0000000UL, /* Peripheral block */
49 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
51 PTE_BLOCK_PXN | PTE_BLOCK_UXN
58 struct mm_region *mem_map = hikey_mem_map;
60 int board_early_init_f(void)
72 gd->ram_size = PHYS_SDRAM_1_SIZE;
77 int dram_init_banksize(void)
79 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
80 gd->bd->bi_dram[0].size = gd->ram_size;
85 void hikey960_sd_init(void)
90 data = readl(SCTRL_SCFPLLCTRL0);
91 data |= SCTRL_SCFPLLCTRL0_FPLL0_EN;
92 writel(data, SCTRL_SCFPLLCTRL0);
95 data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x79)) &
98 writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x79));
100 data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x78));
102 writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x78));
107 data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6b)) &
110 writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6b));
112 data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6a));
114 writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6a));
119 writel(0, PINMUX4_SDDET);
122 writel(15 << 4, PINCONF3_SDCLK);
123 writel((1 << 0) | (8 << 4), PINCONF3_SDCMD);
124 writel((1 << 0) | (8 << 4), PINCONF3_SDDATA0);
125 writel((1 << 0) | (8 << 4), PINCONF3_SDDATA1);
126 writel((1 << 0) | (8 << 4), PINCONF3_SDDATA2);
127 writel((1 << 0) | (8 << 4), PINCONF3_SDDATA3);
129 /* Set SD clock mux */
131 data = readl(CRG_REG_BASE + 0xb8);
132 data |= ((1 << 6) | (1 << 6 << 16) | (0 << 4) | (3 << 4 << 16));
133 writel(data, CRG_REG_BASE + 0xb8);
135 data = readl(CRG_REG_BASE + 0xb8);
136 } while ((data & ((1 << 6) | (3 << 4))) != ((1 << 6) | (0 << 4)));
138 /* Take SD out of reset */
139 writel(1 << 18, CRG_PERRSTDIS4);
141 data = readl(CRG_PERRSTSTAT4);
142 } while ((data & (1 << 18)) == (1 << 18));
144 /* Enable hclk_gate_sd */
145 data = readl(CRG_REG_BASE + 0);
147 writel(data, CRG_REG_BASE + 0);
149 /* Enable clk_andgt_mmc */
150 data = readl(CRG_REG_BASE + 0xf4);
151 data |= ((1 << 3) | (1 << 3 << 16));
152 writel(data, CRG_REG_BASE + 0xf4);
154 /* Enable clk_gate_sd */
155 data = readl(CRG_PEREN4);
157 writel(data, CRG_PEREN4);
159 data = readl(CRG_PERCLKEN4);
160 } while ((data & (1 << 17)) != (1 << 17));
163 static void show_psci_version(void)
165 struct arm_smccc_res res;
167 arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
169 printf("PSCI: v%ld.%ld\n",
170 PSCI_VERSION_MAJOR(res.a0),
171 PSCI_VERSION_MINOR(res.a0));
184 void reset_cpu(ulong addr)