2 * (C) Copyright 2015 Linaro
3 * Peter Griffin <peter.griffin@linaro.org>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <dm/platform_data/serial_pl01x.h>
15 #include <power/hi6553_pmic.h>
16 #include <asm-generic/gpio.h>
17 #include <asm/arch/dwmmc.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/periph.h>
20 #include <asm/arch/pinmux.h>
21 #include <asm/arch/hi6220.h>
22 #include <asm/armv8/mmu.h>
24 /*TODO drop this table in favour of device tree */
25 static const struct hikey_gpio_platdata hi6220_gpio[] = {
26 { 0, HI6220_GPIO_BASE(0)},
27 { 1, HI6220_GPIO_BASE(1)},
28 { 2, HI6220_GPIO_BASE(2)},
29 { 3, HI6220_GPIO_BASE(3)},
30 { 4, HI6220_GPIO_BASE(4)},
31 { 5, HI6220_GPIO_BASE(5)},
32 { 6, HI6220_GPIO_BASE(6)},
33 { 7, HI6220_GPIO_BASE(7)},
34 { 8, HI6220_GPIO_BASE(8)},
35 { 9, HI6220_GPIO_BASE(9)},
36 { 10, HI6220_GPIO_BASE(10)},
37 { 11, HI6220_GPIO_BASE(11)},
38 { 12, HI6220_GPIO_BASE(12)},
39 { 13, HI6220_GPIO_BASE(13)},
40 { 14, HI6220_GPIO_BASE(14)},
41 { 15, HI6220_GPIO_BASE(15)},
42 { 16, HI6220_GPIO_BASE(16)},
43 { 17, HI6220_GPIO_BASE(17)},
44 { 18, HI6220_GPIO_BASE(18)},
45 { 19, HI6220_GPIO_BASE(19)},
49 U_BOOT_DEVICES(hi6220_gpios) = {
50 { "gpio_hi6220", &hi6220_gpio[0] },
51 { "gpio_hi6220", &hi6220_gpio[1] },
52 { "gpio_hi6220", &hi6220_gpio[2] },
53 { "gpio_hi6220", &hi6220_gpio[3] },
54 { "gpio_hi6220", &hi6220_gpio[4] },
55 { "gpio_hi6220", &hi6220_gpio[5] },
56 { "gpio_hi6220", &hi6220_gpio[6] },
57 { "gpio_hi6220", &hi6220_gpio[7] },
58 { "gpio_hi6220", &hi6220_gpio[8] },
59 { "gpio_hi6220", &hi6220_gpio[9] },
60 { "gpio_hi6220", &hi6220_gpio[10] },
61 { "gpio_hi6220", &hi6220_gpio[11] },
62 { "gpio_hi6220", &hi6220_gpio[12] },
63 { "gpio_hi6220", &hi6220_gpio[13] },
64 { "gpio_hi6220", &hi6220_gpio[14] },
65 { "gpio_hi6220", &hi6220_gpio[15] },
66 { "gpio_hi6220", &hi6220_gpio[16] },
67 { "gpio_hi6220", &hi6220_gpio[17] },
68 { "gpio_hi6220", &hi6220_gpio[18] },
69 { "gpio_hi6220", &hi6220_gpio[19] },
72 DECLARE_GLOBAL_DATA_PTR;
74 static const struct pl01x_serial_platdata serial_platdata = {
75 #if CONFIG_CONS_INDEX == 1
76 .base = HI6220_UART0_BASE,
77 #elif CONFIG_CONS_INDEX == 4
78 .base = HI6220_UART3_BASE,
80 #error "Unsuported console index value."
86 U_BOOT_DEVICE(hikey_seriala) = {
87 .name = "serial_pl01x",
88 .platdata = &serial_platdata,
91 static struct mm_region hikey_mem_map[] = {
95 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
100 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
101 PTE_BLOCK_NON_SHARE |
102 PTE_BLOCK_PXN | PTE_BLOCK_UXN
104 /* List terminator */
109 struct mm_region *mem_map = hikey_mem_map;
111 #ifdef CONFIG_BOARD_EARLY_INIT_F
112 int board_uart_init(void)
114 switch (CONFIG_CONS_INDEX) {
116 hi6220_pinmux_config(PERIPH_ID_UART0);
119 hi6220_pinmux_config(PERIPH_ID_UART3);
122 debug("%s: Unsupported UART selected\n", __func__);
129 int board_early_init_f(void)
136 struct peri_sc_periph_regs *peri_sc =
137 (struct peri_sc_periph_regs *)HI6220_PERI_BASE;
139 struct alwayson_sc_regs *ao_sc =
140 (struct alwayson_sc_regs *)ALWAYSON_CTRL_BASE;
142 /* status offset from enable reg */
143 #define STAT_EN_OFF 0x2
145 void hi6220_clk_enable(u32 bitfield, unsigned int *clk_base)
149 data = readl(clk_base);
152 writel(bitfield, clk_base);
154 data = readl(clk_base + STAT_EN_OFF);
155 } while ((data & bitfield) == 0);
158 /* status offset from disable reg */
159 #define STAT_DIS_OFF 0x1
161 void hi6220_clk_disable(u32 bitfield, unsigned int *clk_base)
165 data = readl(clk_base);
168 writel(data, clk_base);
170 data = readl(clk_base + STAT_DIS_OFF);
171 } while (data & bitfield);
174 #define EYE_PATTERN 0x70533483
176 int board_usb_init(int index, enum usb_init_type init)
180 /* enable USB clock */
181 hi6220_clk_enable(PERI_CLK0_USBOTG, &peri_sc->clk0_en);
183 /* take usb IPs out of reset */
184 writel(PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
185 PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K,
188 data = readl(&peri_sc->rst0_stat);
189 data &= PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
190 PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K;
194 data = readl(&peri_sc->ctrl5);
195 data &= ~PERI_CTRL5_PICOPHY_BC_MODE;
196 data |= PERI_CTRL5_USBOTG_RES_SEL | PERI_CTRL5_PICOPHY_ACAENB;
198 writel(data, &peri_sc->ctrl5);
202 /* configure USB PHY */
203 data = readl(&peri_sc->ctrl4);
205 /* make PHY out of low power mode */
206 data &= ~PERI_CTRL4_PICO_SIDDQ;
207 data &= ~PERI_CTRL4_PICO_OGDISABLE;
208 data |= PERI_CTRL4_PICO_VBUSVLDEXTSEL | PERI_CTRL4_PICO_VBUSVLDEXT;
209 writel(data, &peri_sc->ctrl4);
211 writel(EYE_PATTERN, &peri_sc->ctrl8);
217 static int config_sd_carddetect(void)
221 /* configure GPIO8 as nopull */
222 writel(0, 0xf8001830);
224 gpio_request(8, "SD CD");
226 gpio_direction_input(8);
227 ret = gpio_get_value(8);
230 printf("%s: SD card present\n", __func__);
234 printf("%s: SD card not present\n", __func__);
239 static void mmc1_init_pll(void)
243 /* select SYSPLL as the source of MMC1 */
244 /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */
245 writel(1 << 11 | 1 << 27, &peri_sc->clk0_sel);
247 data = readl(&peri_sc->clk0_sel);
248 } while (!(data & (1 << 11)));
250 /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */
251 writel(1 << 30, &peri_sc->clk0_sel);
253 data = readl(&peri_sc->clk0_sel);
254 } while (data & (1 << 14));
256 hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
258 hi6220_clk_enable(PERI_CLK12_MMC1_SRC, &peri_sc->clk12_en);
261 /* 1.2GHz / 50 = 24MHz */
262 writel(0x31 | (1 << 7), &peri_sc->clkcfg8bit2);
263 data = readl(&peri_sc->clkcfg8bit2);
264 } while ((data & 0x31) != 0x31);
267 static void mmc1_reset_clk(void)
271 /* disable mmc1 bus clock */
272 hi6220_clk_disable(PERI_CLK0_MMC1, &peri_sc->clk0_dis);
274 /* enable mmc1 bus clock */
275 hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
277 /* reset mmc1 clock domain */
278 writel(PERI_RST0_MMC1, &peri_sc->rst0_en);
280 /* bypass mmc1 clock phase */
281 data = readl(&peri_sc->ctrl2);
283 writel(data, &peri_sc->ctrl2);
285 /* disable low power */
286 data = readl(&peri_sc->ctrl13);
288 writel(data, &peri_sc->ctrl13);
290 data = readl(&peri_sc->rst0_stat);
291 } while (!(data & PERI_RST0_MMC1));
293 /* unreset mmc0 clock domain */
294 writel(PERI_RST0_MMC1, &peri_sc->rst0_dis);
296 data = readl(&peri_sc->rst0_stat);
297 } while (data & PERI_RST0_MMC1);
300 /* PMU SSI is the IP that maps the external PMU hi6553 registers as IO */
301 static void hi6220_pmussi_init(void)
305 /* Take PMUSSI out of reset */
306 writel(ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N,
309 data = readl(&ao_sc->rst4_stat);
310 } while (data & ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N);
312 /* set PMU SSI clock latency for read operation */
313 data = readl(&ao_sc->mcu_subsys_ctrl3);
314 data &= ~ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK;
315 data |= ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3;
316 writel(data, &ao_sc->mcu_subsys_ctrl3);
318 /* enable PMUSSI clock */
319 data = ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU |
320 ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU;
322 hi6220_clk_enable(data, &ao_sc->clk5_en);
324 /* Output high to PMIC on PWR_HOLD_GPIO0_0 */
325 gpio_request(0, "PWR_HOLD_GPIO0_0");
326 gpio_direction_output(0, 1);
329 int misc_init_r(void)
339 #ifdef CONFIG_GENERIC_MMC
341 static int init_dwmmc(void)
347 /* mmc0 clocks are already configured by ATF */
348 ret = hi6220_pinmux_config(PERIPH_ID_SDMMC0);
350 printf("%s: Error configuring pinmux for eMMC (%d)\n"
353 ret |= hi6220_dwmci_add_port(0, HI6220_MMC0_BASE, 8);
355 printf("%s: Error adding eMMC port (%d)\n", __func__, ret);
358 /* take mmc1 (sd slot) out of reset, configure clocks and pinmuxing */
362 ret |= hi6220_pinmux_config(PERIPH_ID_SDMMC1);
364 printf("%s: Error configuring pinmux for eMMC (%d)\n"
367 config_sd_carddetect();
369 ret |= hi6220_dwmci_add_port(1, HI6220_MMC1_BASE, 4);
371 printf("%s: Error adding SD port (%d)\n", __func__, ret);
377 /* setup board specific PMIC */
378 int power_init_board(void)
380 /* init the hi6220 pmussi ip */
381 hi6220_pmussi_init();
383 power_hi6553_init((u8 *)HI6220_PMUSSI_BASE);
388 int board_mmc_init(bd_t *bis)
392 /* add the eMMC and sd ports */
396 debug("init_dwmmc failed\n");
404 gd->ram_size = PHYS_SDRAM_1_SIZE;
408 void dram_init_banksize(void)
410 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
411 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
414 /* Use the Watchdog to cause reset */
415 void reset_cpu(ulong addr)
417 /* TODO program the watchdog */