2 * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
3 * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <power/pmic.h>
31 #include <asm/arch/clock.h>
32 #include <asm/arch/sys_proto.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 #define BOARD_STRING "Board: HALE TT-01"
40 /* Clock configuration */
41 #define CCM_CCMR_SETUP 0x074B0BF5
43 static void board_setup_clocks(void)
45 struct clock_control_regs *ccm = (struct clock_control_regs *) CCM_BASE;
46 volatile int wait = 0x10000;
48 writel(CCM_CCMR_SETUP, &ccm->ccmr);
52 writel(CCM_CCMR_SETUP | CCMR_MPE, &ccm->ccmr);
53 writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr);
55 /* Set up clock to 532MHz */
56 writel(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) |
57 PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |
58 PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |
59 PDR0_MCU_PODF(0), &ccm->pdr0);
60 writel(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | PLL_MFN(12),
62 writel(PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1),
66 /* DRAM configuration */
68 #define ESDMISC_MDDR_SETUP 0x00000004
69 #define ESDMISC_MDDR_RESET_DL 0x0000000c
71 * decoding magic 0x6ac73a = 0b 0110 1010 1100 0111 0011 1010 below:
72 * tXP = 11, tWTR = 0, tRP = 10, tMRD = 10
73 * tWR = 1, tRAS = 100, tRRD = 01, tCAS = 11
74 * tRCD = 011, tRC = 010
75 * note: all but tWTR (1), tRC (111) are reset defaults,
76 * the same values work in the jtag configuration
78 * Bluetechnix setup has 0x75e73a (for 128MB) =
79 * 0b 0111 0101 1110 0111 0011 1010
80 * tXP = 11, tWTR = 1, tRP = 01, tMRD = 01
81 * tWR = 1, tRAS = 110, tRRD = 01, tCAS = 11
82 * tRCD = 011, tRC = 010
84 #define ESDCFG0_MDDR_SETUP 0x006ac73a
85 #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
86 #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
87 ESDCTL_DSIZ(2) | ESDCTL_BL(1))
88 #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
89 #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
90 #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
91 #define ESDCTL_RW ESDCTL_SETTINGS
93 static void board_setup_sdram(void)
96 struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
99 * setup pad control for the controller pins
100 * no loopback, no pull, no keeper, no open drain,
101 * standard input, standard drive, slow slew rate
103 for (pad = (u32 *) IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B;
104 pad <= (u32 *) IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0; pad++)
107 /* set up MX31 DDR Memory Controller */
108 writel(ESDMISC_MDDR_SETUP, &esdc->misc);
109 writel(ESDCFG0_MDDR_SETUP, &esdc->cfg0);
111 /* perform DDR init sequence for CSD0 */
112 writel(ESDCTL_PRECHARGE, &esdc->ctl0);
113 writel(0x12344321, CSD0_BASE+0x0f00);
114 writel(ESDCTL_AUTOREFRESH, &esdc->ctl0);
115 writel(0x12344321, CSD0_BASE);
116 writel(0x12344321, CSD0_BASE);
117 writel(ESDCTL_LOADMODEREG, &esdc->ctl0);
118 writeb(0xda, CSD0_BASE+0x33);
119 writeb(0xff, CSD0_BASE+0x1000000);
120 writel(ESDCTL_RW, &esdc->ctl0);
121 writel(0xDEADBEEF, CSD0_BASE);
122 writel(ESDMISC_MDDR_RESET_DL, &esdc->misc);
125 static void tt01_spi3_hw_init(void)
128 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MISO, MUX_CTL_FUNC));
129 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MOSI, MUX_CTL_FUNC));
130 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_SCLK, MUX_CTL_FUNC));
131 /* CSPI3, SS0 = Atlas */
132 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_ALT1));
134 /* start CSPI3 clock (3 = always on except if PLL off) */
135 setbits_le32(CCM_CGR0, 3 << 16);
140 /* dram_init must store complete ramsize in gd->ram_size */
141 gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE,
146 int board_early_init_f(void)
148 /* CS4: FPGA incl. network controller */
149 struct mxc_weimcs cs4 = {
150 /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
151 CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6),
152 /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
153 CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
154 /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
155 CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
158 /* this seems essential, won't start without, but why? */
159 writel(IPU_CONF_DI_EN, (u32 *) IPU_CONF);
161 board_setup_clocks();
163 mxc_setup_weimcs(4, &cs4);
165 /* Setup UART2 and SPI3 pins */
166 mx31_uart2_hw_init();
174 /* address of boot parameters */
175 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
179 int board_late_init(void)
181 #ifdef CONFIG_HW_WATCHDOG
190 puts(BOARD_STRING "\n");
194 #ifdef CONFIG_MXC_MMC
195 int board_mmc_init(bd_t *bis)
202 * this is the first driver to use the pmic, so call
203 * pmic_init() here. board_late_init() is too late for
207 ret = pmic_init(I2C_PMIC);
211 p = pmic_get("FSL_PMIC");
215 /* configure pins for SDHC1 only */
216 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_CLK, MUX_CTL_FUNC));
217 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_CMD, MUX_CTL_FUNC));
218 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA0, MUX_CTL_FUNC));
219 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA1, MUX_CTL_FUNC));
220 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA2, MUX_CTL_FUNC));
221 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA3, MUX_CTL_FUNC));
223 /* turn on power V_MMC1 */
224 if (pmic_reg_read(p, REG_MODE_1, &val) < 0)
225 pmic_reg_write(p, REG_MODE_1, val | VMMC1EN);
227 return mxc_mmc_init(bis);
231 int board_eth_init(bd_t *bis)
234 #ifdef CONFIG_SMC911X
235 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
240 #ifdef CONFIG_CONSOLE_EXTRA_INFO
241 void video_get_info_str(int line_number, char *info)
243 u32 srev = get_cpu_rev();
245 switch (line_number) {
247 sprintf(info, " CPU : Freescale i.MX31 rev %d.%d%s at %d MHz",
248 (srev & 0xF0) >> 4, (srev & 0x0F),
249 ((srev & 0x8000) ? " unknown" : ""),
250 mxc_get_clock(MXC_ARM_CLK) / 1000000);
253 strcpy(info, " " BOARD_STRING);