board/gumstix/pepper/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Board functions for Gumstix Pepper and AM335x-based boards
   4  *
   5  * Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
   6  * Based on board/ti/am335x/board.c from Texas Instruments, Inc.
   7  */
   8
   9 #include <common.h>
  10 #include <env.h>
  11 #include <errno.h>
  12 #include <init.h>
  13 #include <net.h>
  14 #include <serial.h>
  15 #include <spl.h>
  16 #include <asm/arch/cpu.h>
  17 #include <asm/arch/hardware.h>
  18 #include <asm/arch/omap.h>
  19 #include <asm/arch/ddr_defs.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/gpio.h>
  22 #include <asm/arch/mmc_host_def.h>
  23 #include <asm/arch/sys_proto.h>
  24 #include <asm/arch/mem.h>
  25 #include <asm/io.h>
  26 #include <asm/emif.h>
  27 #include <asm/gpio.h>
  28 #include <i2c.h>
  29 #include <miiphy.h>
  30 #include <cpsw.h>
  31 #include <power/tps65217.h>
  32 #include <watchdog.h>
  33 #include "board.h"
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #ifdef CONFIG_SPL_BUILD
  38 #define OSC     (V_OSCK/1000000)
  39
  40 static const struct ddr_data ddr3_data = {
  41         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  42         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  43         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  44         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  45 };
  46
  47 static const struct cmd_control ddr3_cmd_ctrl_data = {
  48         .cmd0csratio = MT41K256M16HA125E_RATIO,
  49         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  50
  51         .cmd1csratio = MT41K256M16HA125E_RATIO,
  52         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  53
  54         .cmd2csratio = MT41K256M16HA125E_RATIO,
  55         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  56 };
  57
  58 static struct emif_regs ddr3_emif_reg_data = {
  59         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  60         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  61         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  62         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  63         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  64         .zq_config = MT41K256M16HA125E_ZQ_CFG,
  65         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  66 };
  67
  68 const struct dpll_params dpll_ddr3 = {400, OSC-1, 1, -1, -1, -1, -1};
  69
  70 const struct ctrl_ioregs ioregs_ddr3 = {
  71         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
  72         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
  73         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
  74         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
  75         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
  76 };
  77
  78 static const struct ddr_data ddr2_data = {
  79         .datardsratio0 = MT47H128M16RT25E_RD_DQS,
  80         .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
  81         .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
  82 };
  83
  84 static const struct cmd_control ddr2_cmd_ctrl_data = {
  85         .cmd0csratio = MT47H128M16RT25E_RATIO,
  86
  87         .cmd1csratio = MT47H128M16RT25E_RATIO,
  88
  89         .cmd2csratio = MT47H128M16RT25E_RATIO,
  90 };
  91
  92 static const struct emif_regs ddr2_emif_reg_data = {
  93         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
  94         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
  95         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
  96         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
  97         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
  98         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
  99 };
 100
 101 const struct dpll_params dpll_ddr2 = {266, OSC-1, 1, -1, -1, -1, -1};
 102
 103 const struct ctrl_ioregs ioregs_ddr2 = {
 104         .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 105         .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 106         .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 107         .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 108         .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 109 };
 110
 111 static int read_eeprom(struct pepper_board_id *header)
 112 {
 113         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
 114                 return -ENODEV;
 115         }
 116
 117         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
 118                 sizeof(struct pepper_board_id))) {
 119                 return -EIO;
 120         }
 121
 122         return 0;
 123 }
 124
 125 const struct dpll_params *get_dpll_ddr_params(void)
 126 {
 127         struct pepper_board_id header;
 128
 129         enable_i2c0_pin_mux();
 130         i2c_set_bus_num(0);
 131
 132         if (read_eeprom(&header) < 0)
 133                 return &dpll_ddr3;
 134
 135         switch (header.device_vendor) {
 136         case GUMSTIX_PEPPER:
 137                 return &dpll_ddr2;
 138         case GUMSTIX_PEPPER_DVI:
 139                 return &dpll_ddr3;
 140         default:
 141                 return &dpll_ddr3;
 142         }
 143 }
 144
 145 void sdram_init(void)
 146 {
 147         const struct dpll_params *dpll = get_dpll_ddr_params();
 148
 149         /*
 150          * Here we are assuming PLL clock reveals the type of RAM.
 151          * DDR2 = 266
 152          * DDR3 = 400
 153          * Note that DDR3 is the default.
 154          */
 155         if (dpll->m == 266) {
 156                 config_ddr(dpll->m, &ioregs_ddr2, &ddr2_data,
 157                         &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 158         }
 159         else if (dpll->m == 400) {
 160                 config_ddr(dpll->m, &ioregs_ddr3, &ddr3_data,
 161                         &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 162         }
 163 }
 164
 165 #ifdef CONFIG_SPL_OS_BOOT
 166 int spl_start_uboot(void)
 167 {
 168         /* break into full u-boot on 'c' */
 169         return serial_tstc() && serial_getc() == 'c';
 170 }
 171 #endif
 172
 173 void set_uart_mux_conf(void)
 174 {
 175         enable_uart0_pin_mux();
 176 }
 177
 178 void set_mux_conf_regs(void)
 179 {
 180         enable_board_pin_mux();
 181 }
 182
 183
 184 #endif
 185
 186 int board_init(void)
 187 {
 188 #if defined(CONFIG_HW_WATCHDOG)
 189         hw_watchdog_init();
 190 #endif
 191
 192         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 193         gpmc_init();
 194
 195         return 0;
 196 }
 197
 198 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 199         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 200 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 201
 202 static void cpsw_control(int enabled)
 203 {
 204         /* VTP can be added here */
 205
 206         return;
 207 }
 208
 209 static struct cpsw_slave_data cpsw_slaves[] = {
 210         {
 211                 .slave_reg_ofs  = 0x208,
 212                 .sliver_reg_ofs = 0xd80,
 213                 .phy_addr       = 0,
 214                 .phy_if         = PHY_INTERFACE_MODE_RGMII,
 215         },
 216 };
 217
 218 static struct cpsw_platform_data cpsw_data = {
 219         .mdio_base              = CPSW_MDIO_BASE,
 220         .cpsw_base              = CPSW_BASE,
 221         .mdio_div               = 0xff,
 222         .channels               = 8,
 223         .cpdma_reg_ofs          = 0x800,
 224         .slaves                 = 1,
 225         .slave_data             = cpsw_slaves,
 226         .ale_reg_ofs            = 0xd00,
 227         .ale_entries            = 1024,
 228         .host_port_reg_ofs      = 0x108,
 229         .hw_stats_reg_ofs       = 0x900,
 230         .bd_ram_ofs             = 0x2000,
 231         .mac_control            = (1 << 5),
 232         .control                = cpsw_control,
 233         .host_port_num          = 0,
 234         .version                = CPSW_CTRL_VERSION_2,
 235 };
 236
 237 int board_eth_init(bd_t *bis)
 238 {
 239         int rv, n = 0;
 240         uint8_t mac_addr[6];
 241         uint32_t mac_hi, mac_lo;
 242         const char *devname;
 243
 244         if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
 245                 /* try reading mac address from efuse */
 246                 mac_lo = readl(&cdev->macid0l);
 247                 mac_hi = readl(&cdev->macid0h);
 248                 mac_addr[0] = mac_hi & 0xFF;
 249                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 250                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 251                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 252                 mac_addr[4] = mac_lo & 0xFF;
 253                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 254                 if (is_valid_ethaddr(mac_addr))
 255                         eth_env_set_enetaddr("ethaddr", mac_addr);
 256         }
 257
 258         writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
 259
 260         rv = cpsw_register(&cpsw_data);
 261         if (rv < 0)
 262                 printf("Error %d registering CPSW switch\n", rv);
 263         else
 264                 n += rv;
 265
 266         /*
 267          *
 268          * CPSW RGMII Internal Delay Mode is not supported in all PVT
 269          * operating points.  So we must set the TX clock delay feature
 270          * in the KSZ9021 PHY.  Since we only support a single ethernet
 271          * device in U-Boot, we only do this for the current instance.
 272          */
 273         devname = miiphy_get_current_dev();
 274         /* max rx/tx clock delay, min rx/tx control delay */
 275         miiphy_write(devname, 0x0, 0x0b, 0x8104);
 276         miiphy_write(devname, 0x0, 0xc, 0xa0a0);
 277
 278         /* min rx data delay */
 279         miiphy_write(devname, 0x0, 0x0b, 0x8105);
 280         miiphy_write(devname, 0x0, 0x0c, 0x0000);
 281
 282         /* min tx data delay */
 283         miiphy_write(devname, 0x0, 0x0b, 0x8106);
 284         miiphy_write(devname, 0x0, 0x0c, 0x0000);
 285
 286         return n;
 287 }
 288 #endif