2 # Copyright (C) 2009 Pegatron Corporation
3 # Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
4 # Copyright (C) 2009-2012 Genesi USA, Inc.
9 # Stefano Babic DENX Software Engineering sbabic@denx.de.
11 # See file CREDITS for list of people who contributed to this
14 # This program is free software; you can redistribute it and/or
15 # modify it under the terms of the GNU General Public License as
16 # published by the Free Software Foundation; either version 2 of
17 # the License or (at your option) any later version.
19 # This program is distributed in the hope that it will be useful,
20 # but WITHOUT ANY WARRANTY; without even the implied warranty of
21 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 # GNU General Public License for more details.
24 # You should have received a copy of the GNU General Public License
25 # along with this program; if not write to the Free Software
26 # Foundation Inc. 51 Franklin Street Fifth Floor Boston,
29 # Refer docs/README.imxmage for more details about how-to configure
30 # and create imximage boot image
32 # The syntax is taken as close as possible with the kwbimage
34 # Boot Device : one of
35 # spi, sd (the board has no nand neither onenand)
38 # Device Configuration Data (DCD)
40 # Each entry must have the format:
41 # Addr-type Address Value
44 # Addr-type register length (1,2 or 4 bytes)
45 # Address absolute address of the register
46 # value value to be stored in the register
48 # DDR bus IOMUX PAD settings
49 DATA 4 0x73fa88a0 0x200 # GRP_INMODE1
50 DATA 4 0x73fa850c 0x20c5 # SDODT1
51 DATA 4 0x73fa8510 0x20c5 # SDODT0
52 DATA 4 0x73fa8848 0x4 # DDR_A1
53 DATA 4 0x73fa84b8 0xe7 # DRAM_SDCLK
54 DATA 4 0x73fa84bc 0x45 # DRAM_SDQS0
55 DATA 4 0x73fa84c0 0x45 # DRAM_SDQS1
56 DATA 4 0x73fa84c4 0x45 # DRAM_SDQS2
57 DATA 4 0x73fa84c8 0x45 # DRAM_SDQS3
58 DATA 4 0x73fa8820 0x0 # DDRPKS
59 DATA 4 0x73fa84ac 0xe5 # SDWE
60 DATA 4 0x73fa84b0 0xe5 # SDCKE0
61 DATA 4 0x73fa84b4 0xe5 # SDCKE1
62 DATA 4 0x73fa84cc 0xe5 # DRAM_CS0
63 DATA 4 0x73fa84d0 0xe4 # DRAM_CS1
65 # Setting DDR for micron
66 # 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
69 DATA 4 0x83fd9000 0x82a20000
71 DATA 4 0x83fd9008 0x82a20000
73 DATA 4 0x83fd9010 0xcaaaf6d0
75 DATA 4 0x83fd9004 0x333574aa
77 DATA 4 0x83fd900c 0x333574aa
81 DATA 4 0x83fd9014 0x04008008
82 DATA 4 0x83fd9014 0x0000801a
83 DATA 4 0x83fd9014 0x0000801b
84 DATA 4 0x83fd9014 0x00448019
85 DATA 4 0x83fd9014 0x07328018
86 DATA 4 0x83fd9014 0x04008008
87 DATA 4 0x83fd9014 0x00008010
88 DATA 4 0x83fd9014 0x00008010
89 DATA 4 0x83fd9014 0x06328018
90 DATA 4 0x83fd9014 0x03808019
91 DATA 4 0x83fd9014 0x00408019
92 DATA 4 0x83fd9014 0x00008000
95 DATA 4 0x83fd9014 0x0400800c
96 DATA 4 0x83fd9014 0x0000801e
97 DATA 4 0x83fd9014 0x0000801f
98 DATA 4 0x83fd9014 0x0000801d
99 DATA 4 0x83fd9014 0x0732801c
100 DATA 4 0x83fd9014 0x0400800c
101 DATA 4 0x83fd9014 0x00008014
102 DATA 4 0x83fd9014 0x00008014
103 DATA 4 0x83fd9014 0x0632801c
104 DATA 4 0x83fd9014 0x0380801d
105 DATA 4 0x83fd9014 0x0042801d
106 DATA 4 0x83fd9014 0x00008004
109 DATA 4 0x83fd9000 0xb2a20000
111 DATA 4 0x83fd9008 0xb2a20000
113 DATA 4 0x83fd9010 0xcaaaf6d0
115 DATA 4 0x83fd9034 0x90000000
116 DATA 4 0x83fd9014 0x00000000