2 * Copyright (C) 2009 Freescale Semiconductor, Inc.
3 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
4 * Copyright (C) 2009-2012 Genesi USA, Inc.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/iomux-mx51.h>
29 #include <asm/errno.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/arch/crm_regs.h>
32 #include <asm/arch/clock.h>
35 #include <fsl_esdhc.h>
40 DECLARE_GLOBAL_DATA_PTR;
43 * Compile-time error checking
45 #ifndef CONFIG_MXC_SPI
46 #error "CONFIG_MXC_SPI not set, this is essential for board's operation!"
52 * Note that we get these revisions here for convenience, but we only set
53 * up for the production model Smarttop (1.3) and Smartbook (2.0).
56 #define EFIKAMX_BOARD_REV_11 0x1
57 #define EFIKAMX_BOARD_REV_12 0x2
58 #define EFIKAMX_BOARD_REV_13 0x3
59 #define EFIKAMX_BOARD_REV_14 0x4
61 #define EFIKASB_BOARD_REV_13 0x1
62 #define EFIKASB_BOARD_REV_20 0x2
65 * Board identification
67 static u32 get_mx_rev(void)
80 * + note: r1.1 does not strap this pin properly so it needs to
81 * be hacked or ignored.
84 /* set to 1 in order to get correct value on board rev 1.1 */
85 gpio_direction_output(IMX_GPIO_NR(3, 16), 1);
86 gpio_direction_input(IMX_GPIO_NR(3, 11));
87 gpio_direction_input(IMX_GPIO_NR(3, 16));
88 gpio_direction_input(IMX_GPIO_NR(3, 17));
90 rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 16))) << 0;
91 rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 17))) << 1;
92 rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 11))) << 2;
94 return (~rev & 0x7) + 1;
97 static iomux_v3_cfg_t const efikasb_revision_pads[] = {
98 MX51_PAD_EIM_CS3__GPIO2_28,
99 MX51_PAD_EIM_CS4__GPIO2_29,
102 static inline u32 get_sb_rev(void)
106 imx_iomux_v3_setup_multiple_pads(efikasb_revision_pads,
107 ARRAY_SIZE(efikasb_revision_pads));
108 gpio_direction_input(IMX_GPIO_NR(2, 28));
109 gpio_direction_input(IMX_GPIO_NR(2, 29));
111 rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 28))) << 0;
112 rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 29))) << 1;
117 inline uint32_t get_efikamx_rev(void)
119 if (machine_is_efikamx())
121 else if (machine_is_efikasb())
125 u32 get_board_rev(void)
127 return get_cpu_rev() | (get_efikamx_rev() << 8);
131 * DRAM initialization
135 /* dram_init must store complete ramsize in gd->ram_size */
136 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
144 static iomux_v3_cfg_t const efikamx_uart_pads[] = {
145 MX51_PAD_UART1_RXD__UART1_RXD,
146 MX51_PAD_UART1_TXD__UART1_TXD,
147 MX51_PAD_UART1_RTS__UART1_RTS,
148 MX51_PAD_UART1_CTS__UART1_CTS,
154 static iomux_v3_cfg_t const efikamx_spi_pads[] = {
155 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
156 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
157 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
158 MX51_PAD_CSPI1_SS0__GPIO4_24,
159 MX51_PAD_CSPI1_SS1__GPIO4_25,
160 MX51_PAD_GPIO1_6__GPIO1_6,
163 #define EFIKAMX_SPI_SS0 IMX_GPIO_NR(4, 24)
164 #define EFIKAMX_SPI_SS1 IMX_GPIO_NR(4, 25)
165 #define EFIKAMX_PMIC_IRQ IMX_GPIO_NR(1, 6)
170 #ifdef CONFIG_MXC_SPI
171 static void power_init(void)
174 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
180 /* Write needed to Power Gate 2 register */
181 pmic_reg_read(p, REG_POWER_MISC, &val);
183 pmic_reg_write(p, REG_POWER_MISC, val);
185 /* Externally powered */
186 pmic_reg_read(p, REG_CHARGE, &val);
187 val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
188 pmic_reg_write(p, REG_CHARGE, val);
190 /* power up the system first */
191 pmic_reg_write(p, REG_POWER_MISC, PWUP);
193 /* Set core voltage to 1.1V */
194 pmic_reg_read(p, REG_SW_0, &val);
195 val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
196 pmic_reg_write(p, REG_SW_0, val);
198 /* Setup VCC (SW2) to 1.25 */
199 pmic_reg_read(p, REG_SW_1, &val);
200 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
201 pmic_reg_write(p, REG_SW_1, val);
203 /* Setup 1V2_DIG1 (SW3) to 1.25 */
204 pmic_reg_read(p, REG_SW_2, &val);
205 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
206 pmic_reg_write(p, REG_SW_2, val);
209 /* Raise the core frequency to 800MHz */
210 writel(0x0, &mxc_ccm->cacrr);
212 /* Set switchers in Auto in NORMAL mode & STANDBY mode */
213 /* Setup the switcher mode for SW1 & SW2*/
214 pmic_reg_read(p, REG_SW_4, &val);
215 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
216 (SWMODE_MASK << SWMODE2_SHIFT)));
217 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
218 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
219 pmic_reg_write(p, REG_SW_4, val);
221 /* Setup the switcher mode for SW3 & SW4 */
222 pmic_reg_read(p, REG_SW_5, &val);
223 val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
224 (SWMODE_MASK << SWMODE4_SHIFT)));
225 val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
226 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
227 pmic_reg_write(p, REG_SW_5, val);
229 /* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */
230 pmic_reg_read(p, REG_SETTING_0, &val);
231 val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
232 val |= VDIG_1_8 | VGEN3_1_8 | VCAM_2_6;
233 pmic_reg_write(p, REG_SETTING_0, val);
235 /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
236 pmic_reg_read(p, REG_SETTING_1, &val);
237 val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
238 val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775 | VGEN1_1_2 | VGEN2_3_15;
239 pmic_reg_write(p, REG_SETTING_1, val);
241 /* Enable VGEN1, VGEN2, VDIG, VPLL */
242 pmic_reg_read(p, REG_MODE_0, &val);
243 val |= VGEN1EN | VDIGEN | VGEN2EN | VPLLEN;
244 pmic_reg_write(p, REG_MODE_0, val);
246 /* Configure VGEN3 and VCAM regulators to use external PNP */
247 val = VGEN3CONFIG | VCAMCONFIG;
248 pmic_reg_write(p, REG_MODE_1, val);
251 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
252 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
253 VVIDEOEN | VAUDIOEN | VSDEN;
254 pmic_reg_write(p, REG_MODE_1, val);
256 pmic_reg_read(p, REG_POWER_CTL2, &val);
258 pmic_reg_write(p, REG_POWER_CTL2, val);
263 static inline void power_init(void) { }
269 #ifdef CONFIG_FSL_ESDHC
271 struct fsl_esdhc_cfg esdhc_cfg[2] = {
272 {MMC_SDHC1_BASE_ADDR},
273 {MMC_SDHC2_BASE_ADDR},
276 static iomux_v3_cfg_t const efikamx_sdhc1_pads[] = {
277 MX51_PAD_SD1_CMD__SD1_CMD,
278 MX51_PAD_SD1_CLK__SD1_CLK,
279 MX51_PAD_SD1_DATA0__SD1_DATA0,
280 MX51_PAD_SD1_DATA1__SD1_DATA1,
281 MX51_PAD_SD1_DATA2__SD1_DATA2,
282 MX51_PAD_SD1_DATA3__SD1_DATA3,
283 MX51_PAD_GPIO1_1__SD1_WP,
286 #define EFIKAMX_SDHC1_WP IMX_GPIO_NR(1, 1)
288 static iomux_v3_cfg_t const efikamx_sdhc1_cd_pads[] = {
289 MX51_PAD_GPIO1_0__SD1_CD,
290 MX51_PAD_EIM_CS2__SD1_CD,
293 #define EFIKAMX_SDHC1_CD IMX_GPIO_NR(1, 0)
294 #define EFIKASB_SDHC1_CD IMX_GPIO_NR(2, 27)
296 static iomux_v3_cfg_t const efikasb_sdhc2_pads[] = {
297 MX51_PAD_SD2_CMD__SD2_CMD,
298 MX51_PAD_SD2_CLK__SD2_CLK,
299 MX51_PAD_SD2_DATA0__SD2_DATA0,
300 MX51_PAD_SD2_DATA1__SD2_DATA1,
301 MX51_PAD_SD2_DATA2__SD2_DATA2,
302 MX51_PAD_SD2_DATA3__SD2_DATA3,
303 MX51_PAD_GPIO1_7__SD2_WP,
304 MX51_PAD_GPIO1_8__SD2_CD,
307 #define EFIKASB_SDHC2_CD IMX_GPIO_NR(1, 8)
308 #define EFIKASB_SDHC2_WP IMX_GPIO_NR(1, 7)
310 static inline uint32_t efikamx_mmc_getcd(u32 base)
312 if (base == MMC_SDHC1_BASE_ADDR)
313 if (machine_is_efikamx())
314 return EFIKAMX_SDHC1_CD;
316 return EFIKASB_SDHC1_CD;
318 return EFIKASB_SDHC2_CD;
321 int board_mmc_getcd(struct mmc *mmc)
323 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
324 uint32_t cd = efikamx_mmc_getcd(cfg->esdhc_base);
325 int ret = !gpio_get_value(cd);
330 int board_mmc_init(bd_t *bis)
335 * All Efika MX boards use eSDHC1 with a common write-protect GPIO
337 imx_iomux_v3_setup_multiple_pads(efikamx_sdhc1_pads,
338 ARRAY_SIZE(efikamx_sdhc1_pads));
339 gpio_direction_input(EFIKAMX_SDHC1_WP);
342 * Smartbook and Smarttop differ on the location of eSDHC1
343 * carrier-detect GPIO
345 if (machine_is_efikamx()) {
346 imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[0]);
347 gpio_direction_input(EFIKAMX_SDHC1_CD);
348 } else if (machine_is_efikasb()) {
349 imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[1]);
350 gpio_direction_input(EFIKASB_SDHC1_CD);
353 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
354 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
356 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
358 if (machine_is_efikasb()) {
360 imx_iomux_v3_setup_multiple_pads(efikasb_sdhc2_pads,
361 ARRAY_SIZE(efikasb_sdhc2_pads));
362 gpio_direction_input(EFIKASB_SDHC2_CD);
363 gpio_direction_input(EFIKASB_SDHC2_WP);
365 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
375 static iomux_v3_cfg_t const efikamx_pata_pads[] = {
376 MX51_PAD_NANDF_WE_B__PATA_DIOW,
377 MX51_PAD_NANDF_RE_B__PATA_DIOR,
378 MX51_PAD_NANDF_ALE__PATA_BUFFER_EN,
379 MX51_PAD_NANDF_CLE__PATA_RESET_B,
380 MX51_PAD_NANDF_WP_B__PATA_DMACK,
381 MX51_PAD_NANDF_RB0__PATA_DMARQ,
382 MX51_PAD_NANDF_RB1__PATA_IORDY,
383 MX51_PAD_GPIO_NAND__PATA_INTRQ,
384 MX51_PAD_NANDF_CS2__PATA_CS_0,
385 MX51_PAD_NANDF_CS3__PATA_CS_1,
386 MX51_PAD_NANDF_CS4__PATA_DA_0,
387 MX51_PAD_NANDF_CS5__PATA_DA_1,
388 MX51_PAD_NANDF_CS6__PATA_DA_2,
389 MX51_PAD_NANDF_D15__PATA_DATA15,
390 MX51_PAD_NANDF_D14__PATA_DATA14,
391 MX51_PAD_NANDF_D13__PATA_DATA13,
392 MX51_PAD_NANDF_D12__PATA_DATA12,
393 MX51_PAD_NANDF_D11__PATA_DATA11,
394 MX51_PAD_NANDF_D10__PATA_DATA10,
395 MX51_PAD_NANDF_D9__PATA_DATA9,
396 MX51_PAD_NANDF_D8__PATA_DATA8,
397 MX51_PAD_NANDF_D7__PATA_DATA7,
398 MX51_PAD_NANDF_D6__PATA_DATA6,
399 MX51_PAD_NANDF_D5__PATA_DATA5,
400 MX51_PAD_NANDF_D4__PATA_DATA4,
401 MX51_PAD_NANDF_D3__PATA_DATA3,
402 MX51_PAD_NANDF_D2__PATA_DATA2,
403 MX51_PAD_NANDF_D1__PATA_DATA1,
404 MX51_PAD_NANDF_D0__PATA_DATA0,
410 #ifdef CONFIG_CMD_USB
411 extern void setup_iomux_usb(void);
413 static inline void setup_iomux_usb(void) { }
419 * Smarttop LED pad config is done in the DCD
422 #define EFIKAMX_LED_BLUE IMX_GPIO_NR(3, 13)
423 #define EFIKAMX_LED_GREEN IMX_GPIO_NR(3, 14)
424 #define EFIKAMX_LED_RED IMX_GPIO_NR(3, 15)
426 static iomux_v3_cfg_t const efikasb_led_pads[] = {
427 MX51_PAD_GPIO1_3__GPIO1_3,
428 MX51_PAD_EIM_CS0__GPIO2_25,
431 #define EFIKASB_CAPSLOCK_LED IMX_GPIO_NR(2, 25)
432 #define EFIKASB_MESSAGE_LED IMX_GPIO_NR(1, 3) /* Note: active low */
435 * Board initialization
437 int board_early_init_f(void)
439 if (machine_is_efikasb()) {
440 imx_iomux_v3_setup_multiple_pads(efikasb_led_pads,
441 ARRAY_SIZE(efikasb_led_pads));
442 gpio_direction_output(EFIKASB_CAPSLOCK_LED, 0);
443 gpio_direction_output(EFIKASB_MESSAGE_LED, 1);
444 } else if (machine_is_efikamx()) {
446 * Set up GPIO directions for LEDs.
447 * IOMUX has been done in the DCD already.
448 * Turn the red LED on for pre-relocation code.
450 gpio_direction_output(EFIKAMX_LED_BLUE, 0);
451 gpio_direction_output(EFIKAMX_LED_GREEN, 0);
452 gpio_direction_output(EFIKAMX_LED_RED, 1);
456 * Both these pad configurations for UART and SPI are kind of redundant
457 * since they are the Power-On Defaults for the i.MX51. But, it seems we
458 * should make absolutely sure that they are set up correctly.
460 imx_iomux_v3_setup_multiple_pads(efikamx_uart_pads,
461 ARRAY_SIZE(efikamx_uart_pads));
462 imx_iomux_v3_setup_multiple_pads(efikamx_spi_pads,
463 ARRAY_SIZE(efikamx_spi_pads));
465 /* not technically required for U-Boot operation but do it anyway. */
466 gpio_direction_input(EFIKAMX_PMIC_IRQ);
467 /* Deselect both CS for now, otherwise NOR doesn't probe properly. */
468 gpio_direction_output(EFIKAMX_SPI_SS0, 0);
469 gpio_direction_output(EFIKAMX_SPI_SS1, 1);
476 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
481 int board_late_init(void)
483 if (machine_is_efikamx()) {
485 * Set up Blue LED for "In U-Boot" status.
486 * We're all relocated and ready to U-Boot!
488 gpio_set_value(EFIKAMX_LED_RED, 0);
489 gpio_set_value(EFIKAMX_LED_GREEN, 0);
490 gpio_set_value(EFIKAMX_LED_BLUE, 1);
495 imx_iomux_v3_setup_multiple_pads(efikamx_pata_pads,
496 ARRAY_SIZE(efikamx_pata_pads));
504 u32 rev = get_efikamx_rev();
506 printf("Board: Genesi Efika MX ");
507 if (machine_is_efikamx())
508 printf("Smarttop (1.%i)\n", rev & 0xf);
509 else if (machine_is_efikasb())
510 printf("Smartbook\n");