2 * Copyright (C) 2009 Freescale Semiconductor, Inc.
3 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
4 * Copyright (C) 2009-2012 Genesi USA, Inc.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/iomux-mx51.h>
29 #include <asm/errno.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/arch/crm_regs.h>
32 #include <asm/arch/clock.h>
35 #include <fsl_esdhc.h>
36 #include <power/pmic.h>
40 DECLARE_GLOBAL_DATA_PTR;
43 * Compile-time error checking
45 #ifndef CONFIG_MXC_SPI
46 #error "CONFIG_MXC_SPI not set, this is essential for board's operation!"
52 * Note that we get these revisions here for convenience, but we only set
53 * up for the production model Smarttop (1.3) and Smartbook (2.0).
56 #define EFIKAMX_BOARD_REV_11 0x1
57 #define EFIKAMX_BOARD_REV_12 0x2
58 #define EFIKAMX_BOARD_REV_13 0x3
59 #define EFIKAMX_BOARD_REV_14 0x4
61 #define EFIKASB_BOARD_REV_13 0x1
62 #define EFIKASB_BOARD_REV_20 0x2
65 * Board identification
67 static u32 get_mx_rev(void)
80 * + note: r1.1 does not strap this pin properly so it needs to
81 * be hacked or ignored.
84 /* set to 1 in order to get correct value on board rev 1.1 */
85 gpio_direction_output(IMX_GPIO_NR(3, 16), 1);
86 gpio_direction_input(IMX_GPIO_NR(3, 11));
87 gpio_direction_input(IMX_GPIO_NR(3, 16));
88 gpio_direction_input(IMX_GPIO_NR(3, 17));
90 rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 16))) << 0;
91 rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 17))) << 1;
92 rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 11))) << 2;
94 return (~rev & 0x7) + 1;
97 static iomux_v3_cfg_t const efikasb_revision_pads[] = {
98 MX51_PAD_EIM_CS3__GPIO2_28,
99 MX51_PAD_EIM_CS4__GPIO2_29,
102 static inline u32 get_sb_rev(void)
106 imx_iomux_v3_setup_multiple_pads(efikasb_revision_pads,
107 ARRAY_SIZE(efikasb_revision_pads));
108 gpio_direction_input(IMX_GPIO_NR(2, 28));
109 gpio_direction_input(IMX_GPIO_NR(2, 29));
111 rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 28))) << 0;
112 rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 29))) << 1;
117 inline uint32_t get_efikamx_rev(void)
119 if (machine_is_efikamx())
121 else if (machine_is_efikasb())
125 u32 get_board_rev(void)
127 return get_cpu_rev() | (get_efikamx_rev() << 8);
131 * DRAM initialization
135 /* dram_init must store complete ramsize in gd->ram_size */
136 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
144 static iomux_v3_cfg_t const efikamx_uart_pads[] = {
145 MX51_PAD_UART1_RXD__UART1_RXD,
146 MX51_PAD_UART1_TXD__UART1_TXD,
147 MX51_PAD_UART1_RTS__UART1_RTS,
148 MX51_PAD_UART1_CTS__UART1_CTS,
154 static iomux_v3_cfg_t const efikamx_spi_pads[] = {
155 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
156 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
157 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
158 MX51_PAD_CSPI1_SS0__GPIO4_24,
159 MX51_PAD_CSPI1_SS1__GPIO4_25,
160 MX51_PAD_GPIO1_6__GPIO1_6,
163 #define EFIKAMX_SPI_SS0 IMX_GPIO_NR(4, 24)
164 #define EFIKAMX_SPI_SS1 IMX_GPIO_NR(4, 25)
165 #define EFIKAMX_PMIC_IRQ IMX_GPIO_NR(1, 6)
170 #ifdef CONFIG_MXC_SPI
171 static void power_init(void)
174 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
178 ret = pmic_init(I2C_PMIC);
182 p = pmic_get("FSL_PMIC");
186 /* Write needed to Power Gate 2 register */
187 pmic_reg_read(p, REG_POWER_MISC, &val);
189 pmic_reg_write(p, REG_POWER_MISC, val);
191 /* Externally powered */
192 pmic_reg_read(p, REG_CHARGE, &val);
193 val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
194 pmic_reg_write(p, REG_CHARGE, val);
196 /* power up the system first */
197 pmic_reg_write(p, REG_POWER_MISC, PWUP);
199 /* Set core voltage to 1.1V */
200 pmic_reg_read(p, REG_SW_0, &val);
201 val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
202 pmic_reg_write(p, REG_SW_0, val);
204 /* Setup VCC (SW2) to 1.25 */
205 pmic_reg_read(p, REG_SW_1, &val);
206 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
207 pmic_reg_write(p, REG_SW_1, val);
209 /* Setup 1V2_DIG1 (SW3) to 1.25 */
210 pmic_reg_read(p, REG_SW_2, &val);
211 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
212 pmic_reg_write(p, REG_SW_2, val);
215 /* Raise the core frequency to 800MHz */
216 writel(0x0, &mxc_ccm->cacrr);
218 /* Set switchers in Auto in NORMAL mode & STANDBY mode */
219 /* Setup the switcher mode for SW1 & SW2*/
220 pmic_reg_read(p, REG_SW_4, &val);
221 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
222 (SWMODE_MASK << SWMODE2_SHIFT)));
223 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
224 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
225 pmic_reg_write(p, REG_SW_4, val);
227 /* Setup the switcher mode for SW3 & SW4 */
228 pmic_reg_read(p, REG_SW_5, &val);
229 val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
230 (SWMODE_MASK << SWMODE4_SHIFT)));
231 val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
232 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
233 pmic_reg_write(p, REG_SW_5, val);
235 /* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */
236 pmic_reg_read(p, REG_SETTING_0, &val);
237 val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
238 val |= VDIG_1_8 | VGEN3_1_8 | VCAM_2_6;
239 pmic_reg_write(p, REG_SETTING_0, val);
241 /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
242 pmic_reg_read(p, REG_SETTING_1, &val);
243 val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
244 val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775 | VGEN1_1_2 | VGEN2_3_15;
245 pmic_reg_write(p, REG_SETTING_1, val);
247 /* Enable VGEN1, VGEN2, VDIG, VPLL */
248 pmic_reg_read(p, REG_MODE_0, &val);
249 val |= VGEN1EN | VDIGEN | VGEN2EN | VPLLEN;
250 pmic_reg_write(p, REG_MODE_0, val);
252 /* Configure VGEN3 and VCAM regulators to use external PNP */
253 val = VGEN3CONFIG | VCAMCONFIG;
254 pmic_reg_write(p, REG_MODE_1, val);
257 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
258 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
259 VVIDEOEN | VAUDIOEN | VSDEN;
260 pmic_reg_write(p, REG_MODE_1, val);
262 pmic_reg_read(p, REG_POWER_CTL2, &val);
264 pmic_reg_write(p, REG_POWER_CTL2, val);
269 static inline void power_init(void) { }
275 #ifdef CONFIG_FSL_ESDHC
277 struct fsl_esdhc_cfg esdhc_cfg[2] = {
278 {MMC_SDHC1_BASE_ADDR},
279 {MMC_SDHC2_BASE_ADDR},
282 static iomux_v3_cfg_t const efikamx_sdhc1_pads[] = {
283 MX51_PAD_SD1_CMD__SD1_CMD,
284 MX51_PAD_SD1_CLK__SD1_CLK,
285 MX51_PAD_SD1_DATA0__SD1_DATA0,
286 MX51_PAD_SD1_DATA1__SD1_DATA1,
287 MX51_PAD_SD1_DATA2__SD1_DATA2,
288 MX51_PAD_SD1_DATA3__SD1_DATA3,
289 MX51_PAD_GPIO1_1__SD1_WP,
292 #define EFIKAMX_SDHC1_WP IMX_GPIO_NR(1, 1)
294 static iomux_v3_cfg_t const efikamx_sdhc1_cd_pads[] = {
295 MX51_PAD_GPIO1_0__SD1_CD,
296 NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, MX51_ESDHC_PAD_CTRL),
299 #define EFIKAMX_SDHC1_CD IMX_GPIO_NR(1, 0)
300 #define EFIKASB_SDHC1_CD IMX_GPIO_NR(2, 27)
302 static iomux_v3_cfg_t const efikasb_sdhc2_pads[] = {
303 MX51_PAD_SD2_CMD__SD2_CMD,
304 MX51_PAD_SD2_CLK__SD2_CLK,
305 MX51_PAD_SD2_DATA0__SD2_DATA0,
306 MX51_PAD_SD2_DATA1__SD2_DATA1,
307 MX51_PAD_SD2_DATA2__SD2_DATA2,
308 MX51_PAD_SD2_DATA3__SD2_DATA3,
309 MX51_PAD_GPIO1_7__SD2_WP,
310 MX51_PAD_GPIO1_8__SD2_CD,
313 #define EFIKASB_SDHC2_CD IMX_GPIO_NR(1, 8)
314 #define EFIKASB_SDHC2_WP IMX_GPIO_NR(1, 7)
316 static inline uint32_t efikamx_mmc_getcd(u32 base)
318 if (base == MMC_SDHC1_BASE_ADDR)
319 if (machine_is_efikamx())
320 return EFIKAMX_SDHC1_CD;
322 return EFIKASB_SDHC1_CD;
324 return EFIKASB_SDHC2_CD;
327 int board_mmc_getcd(struct mmc *mmc)
329 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
330 uint32_t cd = efikamx_mmc_getcd(cfg->esdhc_base);
331 int ret = !gpio_get_value(cd);
336 int board_mmc_init(bd_t *bis)
341 * All Efika MX boards use eSDHC1 with a common write-protect GPIO
343 imx_iomux_v3_setup_multiple_pads(efikamx_sdhc1_pads,
344 ARRAY_SIZE(efikamx_sdhc1_pads));
345 gpio_direction_input(EFIKAMX_SDHC1_WP);
348 * Smartbook and Smarttop differ on the location of eSDHC1
349 * carrier-detect GPIO
351 if (machine_is_efikamx()) {
352 imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[0]);
353 gpio_direction_input(EFIKAMX_SDHC1_CD);
354 } else if (machine_is_efikasb()) {
355 imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[1]);
356 gpio_direction_input(EFIKASB_SDHC1_CD);
359 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
360 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
362 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
364 if (machine_is_efikasb()) {
366 imx_iomux_v3_setup_multiple_pads(efikasb_sdhc2_pads,
367 ARRAY_SIZE(efikasb_sdhc2_pads));
368 gpio_direction_input(EFIKASB_SDHC2_CD);
369 gpio_direction_input(EFIKASB_SDHC2_WP);
371 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
381 static iomux_v3_cfg_t const efikamx_pata_pads[] = {
382 MX51_PAD_NANDF_WE_B__PATA_DIOW,
383 MX51_PAD_NANDF_RE_B__PATA_DIOR,
384 MX51_PAD_NANDF_ALE__PATA_BUFFER_EN,
385 MX51_PAD_NANDF_CLE__PATA_RESET_B,
386 MX51_PAD_NANDF_WP_B__PATA_DMACK,
387 MX51_PAD_NANDF_RB0__PATA_DMARQ,
388 MX51_PAD_NANDF_RB1__PATA_IORDY,
389 MX51_PAD_GPIO_NAND__PATA_INTRQ,
390 MX51_PAD_NANDF_CS2__PATA_CS_0,
391 MX51_PAD_NANDF_CS3__PATA_CS_1,
392 MX51_PAD_NANDF_CS4__PATA_DA_0,
393 MX51_PAD_NANDF_CS5__PATA_DA_1,
394 MX51_PAD_NANDF_CS6__PATA_DA_2,
395 MX51_PAD_NANDF_D15__PATA_DATA15,
396 MX51_PAD_NANDF_D14__PATA_DATA14,
397 MX51_PAD_NANDF_D13__PATA_DATA13,
398 MX51_PAD_NANDF_D12__PATA_DATA12,
399 MX51_PAD_NANDF_D11__PATA_DATA11,
400 MX51_PAD_NANDF_D10__PATA_DATA10,
401 MX51_PAD_NANDF_D9__PATA_DATA9,
402 MX51_PAD_NANDF_D8__PATA_DATA8,
403 MX51_PAD_NANDF_D7__PATA_DATA7,
404 MX51_PAD_NANDF_D6__PATA_DATA6,
405 MX51_PAD_NANDF_D5__PATA_DATA5,
406 MX51_PAD_NANDF_D4__PATA_DATA4,
407 MX51_PAD_NANDF_D3__PATA_DATA3,
408 MX51_PAD_NANDF_D2__PATA_DATA2,
409 MX51_PAD_NANDF_D1__PATA_DATA1,
410 MX51_PAD_NANDF_D0__PATA_DATA0,
416 #ifdef CONFIG_CMD_USB
417 extern void setup_iomux_usb(void);
419 static inline void setup_iomux_usb(void) { }
425 * Smarttop LED pad config is done in the DCD
428 #define EFIKAMX_LED_BLUE IMX_GPIO_NR(3, 13)
429 #define EFIKAMX_LED_GREEN IMX_GPIO_NR(3, 14)
430 #define EFIKAMX_LED_RED IMX_GPIO_NR(3, 15)
432 static iomux_v3_cfg_t const efikasb_led_pads[] = {
433 MX51_PAD_GPIO1_3__GPIO1_3,
434 MX51_PAD_EIM_CS0__GPIO2_25,
437 #define EFIKASB_CAPSLOCK_LED IMX_GPIO_NR(2, 25)
438 #define EFIKASB_MESSAGE_LED IMX_GPIO_NR(1, 3) /* Note: active low */
441 * Board initialization
443 int board_early_init_f(void)
445 if (machine_is_efikasb()) {
446 imx_iomux_v3_setup_multiple_pads(efikasb_led_pads,
447 ARRAY_SIZE(efikasb_led_pads));
448 gpio_direction_output(EFIKASB_CAPSLOCK_LED, 0);
449 gpio_direction_output(EFIKASB_MESSAGE_LED, 1);
450 } else if (machine_is_efikamx()) {
452 * Set up GPIO directions for LEDs.
453 * IOMUX has been done in the DCD already.
454 * Turn the red LED on for pre-relocation code.
456 gpio_direction_output(EFIKAMX_LED_BLUE, 0);
457 gpio_direction_output(EFIKAMX_LED_GREEN, 0);
458 gpio_direction_output(EFIKAMX_LED_RED, 1);
462 * Both these pad configurations for UART and SPI are kind of redundant
463 * since they are the Power-On Defaults for the i.MX51. But, it seems we
464 * should make absolutely sure that they are set up correctly.
466 imx_iomux_v3_setup_multiple_pads(efikamx_uart_pads,
467 ARRAY_SIZE(efikamx_uart_pads));
468 imx_iomux_v3_setup_multiple_pads(efikamx_spi_pads,
469 ARRAY_SIZE(efikamx_spi_pads));
471 /* not technically required for U-Boot operation but do it anyway. */
472 gpio_direction_input(EFIKAMX_PMIC_IRQ);
473 /* Deselect both CS for now, otherwise NOR doesn't probe properly. */
474 gpio_direction_output(EFIKAMX_SPI_SS0, 0);
475 gpio_direction_output(EFIKAMX_SPI_SS1, 1);
482 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
487 int board_late_init(void)
489 if (machine_is_efikamx()) {
491 * Set up Blue LED for "In U-Boot" status.
492 * We're all relocated and ready to U-Boot!
494 gpio_set_value(EFIKAMX_LED_RED, 0);
495 gpio_set_value(EFIKAMX_LED_GREEN, 0);
496 gpio_set_value(EFIKAMX_LED_BLUE, 1);
501 imx_iomux_v3_setup_multiple_pads(efikamx_pata_pads,
502 ARRAY_SIZE(efikamx_pata_pads));
510 u32 rev = get_efikamx_rev();
512 printf("Board: Genesi Efika MX ");
513 if (machine_is_efikamx())
514 printf("Smarttop (1.%i)\n", rev & 0xf);
515 else if (machine_is_efikasb())
516 printf("Smartbook\n");