3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 * Keith Outwater, keith_outwater@mvis.com.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * Virtex2 FPGA configuration support for the GEN860T computer
38 #define GEN860T_FPGA_DEBUG
41 #ifdef GEN860T_FPGA_DEBUG
42 #define PRINTF(fmt,args...) printf (fmt ,##args)
44 #define PRINTF(fmt,args...)
48 * Port bit numbers for the Selectmap controls
50 #define FPGA_INIT_BIT_NUM 22 /* PB22 */
51 #define FPGA_RESET_BIT_NUM 11 /* PC11 */
52 #define FPGA_DONE_BIT_NUM 16 /* PB16 */
53 #define FPGA_PROGRAM_BIT_NUM 7 /* PA7 */
55 /* Note that these are pointers to code that is in Flash. They will be
56 * relocated at runtime.
58 Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = {
74 Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
84 * Display FPGA revision information
87 print_fpga_revision(void)
89 vu_long *rev_p = (vu_long *)0x60000008;
91 printf("FPGA Revision 0x%.8lx"
92 " (Date %.2lx/%.2lx/%.2lx, Status \"%.1lx\", Version %.3lu)\n",
94 ((*rev_p >> 28) & 0xf),
95 ((*rev_p >> 20) & 0xff),
96 ((*rev_p >> 12) & 0xff),
97 ((*rev_p >> 8) & 0xf),
103 * Perform a simple test of the FPGA to processor interface using the FPGA's
104 * inverting bus test register. The great thing about doing a read/write
105 * test on a register that inverts it's contents is that you avoid any
106 * problems with bus charging.
107 * Return 0 on failure, 1 on success.
112 vu_long *ibtr_p = (vu_long *)0x60000010;
120 static const ulong bitpattern[] = {
121 0xdeadbeef, /* magic ID pattern for debug */
122 0x00000001, /* single bit */
123 0x00000003, /* two adjacent bits */
124 0x00000007, /* three adjacent bits */
125 0x0000000F, /* four adjacent bits */
126 0x00000005, /* two non-adjacent bits */
127 0x00000015, /* three non-adjacent bits */
128 0x00000055, /* four non-adjacent bits */
129 0xaaaaaaaa, /* alternating 1/0 */
132 for (i = 0; i < 1024; i++) {
133 for (j = 0; j < 31; j++) {
134 for (k = 0; k < sizeof(bitpattern)/sizeof(bitpattern[0]); k++) {
135 *ibtr_p = compare = (bitpattern[k] << j);
137 if (readback != ~compare) {
138 printf("%s:%d: FPGA test fail: expected 0x%.8lx"
140 __FUNCTION__, __LINE__, ~compare, readback);
150 printf("FPGA inverting bus test passed\n");
151 print_fpga_revision();
154 printf("** FPGA inverting bus test failed\n");
161 * Set the active-low FPGA reset signal.
164 fpga_reset(int assert)
166 volatile immap_t *immap = (immap_t *)CFG_IMMR;
168 PRINTF("%s:%d: RESET ", __FUNCTION__, __LINE__);
170 immap->im_ioport.iop_pcdat &= ~(0x8000 >> FPGA_RESET_BIT_NUM);
171 PRINTF("asserted\n");
174 immap->im_ioport.iop_pcdat |= (0x8000 >> FPGA_RESET_BIT_NUM);
175 PRINTF("deasserted\n");
181 * Initialize the SelectMap interface. We assume that the mode and the
182 * initial state of all of the port pins have already been set!
185 fpga_selectmap_init(void)
187 PRINTF("%s:%d: Initialize SelectMap interface\n", __FUNCTION__, __LINE__);
188 fpga_pgm_fn(FALSE, FALSE, 0); /* make sure program pin is inactive */
193 * Initialize the fpga. Return 1 on success, 0 on failure.
196 gen860t_init_fpga(void)
198 DECLARE_GLOBAL_DATA_PTR;
202 PRINTF("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n",
203 __FUNCTION__, __LINE__, gd->reloc_off);
204 fpga_init(gd->reloc_off);
205 fpga_selectmap_init();
207 for(i=0; i < CONFIG_FPGA_COUNT; i++) {
208 PRINTF("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
209 fpga_add(fpga_xilinx, &fpga[i]);
216 * Set the FPGA's active-low SelectMap program line to the specified level
219 fpga_pgm_fn(int assert, int flush, int cookie)
221 volatile immap_t *immap = (immap_t *)CFG_IMMR;
223 PRINTF("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
226 immap->im_ioport.iop_padat &= ~(0x8000 >> FPGA_PROGRAM_BIT_NUM);
227 PRINTF("asserted\n");
230 immap->im_ioport.iop_padat |= (0x8000 >> FPGA_PROGRAM_BIT_NUM);
231 PRINTF("deasserted\n");
238 * Test the state of the active-low FPGA INIT line. Return 1 on INIT
242 fpga_init_fn(int cookie)
244 volatile immap_t *immap = (immap_t *)CFG_IMMR;
246 PRINTF("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
247 if(immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) {
259 * Test the state of the active-high FPGA DONE pin
262 fpga_done_fn(int cookie)
264 volatile immap_t *immap = (immap_t *)CFG_IMMR;
266 PRINTF("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
267 if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_DONE_BIT_NUM)) {
279 * Read FPGA SelectMap data.
282 fpga_read_data_fn(unsigned char *data, int cookie)
284 vu_char *p = (vu_char *)SELECTMAP_BASE;
288 PRINTF("%s: Read 0x%x into 0x%p\n", __FUNCTION__, (int)data, data);
295 * Write data to the FPGA SelectMap port
298 fpga_write_data_fn(unsigned char data, int flush, int cookie)
300 vu_char *p = (vu_char *)SELECTMAP_BASE;
303 PRINTF("%s: Write Data 0x%x\n", __FUNCTION__, (int)data);
311 * Abort and FPGA operation
314 fpga_abort_fn(int cookie)
316 PRINTF("%s:%d: FPGA program sequence aborted\n",
317 __FUNCTION__, __LINE__);
323 * FPGA pre-configuration function. Just make sure that
324 * FPGA reset is asserted to keep the FPGA from starting up after
328 fpga_pre_config_fn(int cookie)
330 PRINTF("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
337 * FPGA post configuration function. Blip the FPGA reset line and then see if
338 * the FPGA appears to be running.
341 fpga_post_config_fn(int cookie)
345 PRINTF("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
352 * Use the FPGA,s inverting bus test register to do a simple test of the
353 * processor interface.
355 rc = test_fpga_ibtr();
361 * Clock, chip select and write signal assert functions and error check
362 * and busy functions. These are only stubs because the GEN860T selectmap
363 * interface handles sequencing of control signals automatically (it uses
364 * a memory-mapped interface to the FPGA SelectMap port). The design of
365 * the interface guarantees that the SelectMap port cannot be overrun so
366 * no busy check is needed. A configuration error is signalled by INIT
367 * going low during configuration, so there is no need for a separate error
371 fpga_clk_fn(int assert_clk, int flush, int cookie)
377 fpga_cs_fn(int assert_cs, int flush, int cookie)
383 fpga_wr_fn(int assert_write, int flush, int cookie)
389 fpga_err_fn(int cookie)
395 fpga_busy_fn(int cookie)
401 /* vim: set ts=4 tw=78 sw=4: */