1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017 General Electric Company
5 * Based on board/freescale/mx53loco/mx53loco.c:
7 * Copyright (C) 2011 Freescale Semiconductor, Inc.
8 * Jason Liu <r64343@freescale.com>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/arch/crm_regs.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/iomux-mx53.h>
19 #include <asm/arch/clock.h>
21 #include <linux/errno.h>
22 #include <linux/libfdt.h>
23 #include <asm/mach-imx/mxc_i2c.h>
24 #include <asm/mach-imx/mx5_video.h>
28 #include <fsl_esdhc_imx.h>
30 #include <power/pmic.h>
31 #include <dialog_pmic.h>
34 #include <ipu_pixfmt.h>
39 #include "../../ge/common/ge_common.h"
40 #include "../../ge/common/vpd_reader.h"
42 #define MX53PPD_LCD_POWER IMX_GPIO_NR(3, 24)
44 DECLARE_GLOBAL_DATA_PTR;
46 static u32 mx53_dram_size[2];
48 phys_size_t get_effective_memsize(void)
51 * WARNING: We must override get_effective_memsize() function here
52 * to report only the size of the first DRAM bank. This is to make
53 * U-Boot relocator place U-Boot into valid memory, that is, at the
54 * end of the first DRAM bank. If we did not override this function
55 * like so, U-Boot would be placed at the address of the first DRAM
56 * bank + total DRAM size - sizeof(uboot), which in the setup where
57 * each DRAM bank contains 512MiB of DRAM would result in placing
58 * U-Boot into invalid memory area close to the end of the first
61 return mx53_dram_size[0];
66 mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
67 mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
69 gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
74 int dram_init_banksize(void)
76 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
77 gd->bd->bi_dram[0].size = mx53_dram_size[0];
79 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
80 gd->bd->bi_dram[1].size = mx53_dram_size[1];
85 u32 get_board_rev(void)
87 return get_cpu_rev() & ~(0xF << 8);
90 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
91 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
93 #ifdef CONFIG_USB_EHCI_MX5
94 int board_ehci_hcd_init(int port)
96 /* request VBUS power enable pin, GPIO7_8 */
97 imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
98 gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
103 static void setup_iomux_fec(void)
105 static const iomux_v3_cfg_t fec_pads[] = {
106 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
107 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP |
109 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
110 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
111 PAD_CTL_HYS | PAD_CTL_PKE),
112 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
113 PAD_CTL_HYS | PAD_CTL_PKE),
114 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
115 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
116 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
117 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
118 PAD_CTL_HYS | PAD_CTL_PKE),
119 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
120 PAD_CTL_HYS | PAD_CTL_PKE),
121 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
122 PAD_CTL_HYS | PAD_CTL_PKE),
125 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
128 static int clock_1GHz(void)
131 u32 ref_clk = MXC_HCLK;
133 * After increasing voltage to 1.25V, we can switch
134 * CPU clock to 1GHz and DDR to 400MHz safely
136 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
138 printf("CPU: Switch CPU clock to 1GHZ failed\n");
142 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
143 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
145 printf("CPU: Switch DDR clock to 400MHz failed\n");
152 void ppd_gpio_init(void)
156 imx_iomux_v3_setup_multiple_pads(ppd_pads, ARRAY_SIZE(ppd_pads));
157 for (i = 0; i < ARRAY_SIZE(ppd_gpios); ++i) {
158 gpio_request(ppd_gpios[i].gpio, "request");
159 gpio_direction_output(ppd_gpios[i].gpio, ppd_gpios[i].value);
163 int board_early_init_f(void)
173 * Do not overwrite the console
174 * Use always serial for U-Boot console
176 int overwrite_console(void)
181 #define VPD_TYPE_INVALID 0x00
182 #define VPD_BLOCK_NETWORK 0x20
183 #define VPD_BLOCK_HWID 0x44
184 #define VPD_PRODUCT_PPD 4
185 #define VPD_HAS_MAC1 0x1
186 #define VPD_MAC_ADDRESS_LENGTH 6
191 unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
195 * Extracts MAC and product information from the VPD.
197 static int vpd_callback(struct vpd_cache *userdata, u8 id, u8 version,
198 u8 type, size_t size, u8 const *data)
200 struct vpd_cache *vpd = userdata;
202 if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
204 vpd->product_id = data[0];
206 } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
207 type != VPD_TYPE_INVALID) {
209 vpd->has |= VPD_HAS_MAC1;
210 memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
217 static void process_vpd(struct vpd_cache *vpd)
221 if (vpd->product_id == VPD_PRODUCT_PPD)
224 if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
225 eth_env_set_enetaddr("ethaddr", vpd->mac1);
230 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
232 mxc_set_sata_internal_clock();
237 int misc_init_r(void)
241 /* We care about WDOG only, treating everything else as
244 if (get_imx_reset_cause() & 0x0010)
249 env_set("bootcause", cause);
254 int board_late_init(void)
257 struct vpd_cache vpd;
259 memset(&vpd, 0, sizeof(vpd));
260 res = read_vpd(&vpd, vpd_callback);
264 printf("Can't read VPD");
279 puts("Board: GE PPD\n");
284 #ifdef CONFIG_OF_BOARD_SETUP
285 int ft_board_setup(void *blob, bd_t *bd)
287 char *rtc_status = env_get("rtc_status");
289 fdt_setprop(blob, 0, "ge,boot-ver", version_string,
290 strlen(version_string) + 1);
292 fdt_setprop(blob, 0, "ge,rtc-status", rtc_status,
293 strlen(rtc_status) + 1);