board/ge/bx50v3/bx50v3.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Timesys Corporation
   4  * Copyright 2015 General Electric Company
   5  * Copyright 2012 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <init.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <env.h>
  14 #include <linux/errno.h>
  15 #include <linux/libfdt.h>
  16 #include <asm/gpio.h>
  17 #include <asm/mach-imx/mxc_i2c.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/mach-imx/boot_mode.h>
  20 #include <asm/mach-imx/video.h>
  21 #include <mmc.h>
  22 #include <fsl_esdhc_imx.h>
  23 #include <miiphy.h>
  24 #include <net.h>
  25 #include <netdev.h>
  26 #include <asm/arch/mxc_hdmi.h>
  27 #include <asm/arch/crm_regs.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/sys_proto.h>
  30 #include <i2c.h>
  31 #include <input.h>
  32 #include <pwm.h>
  33 #include <version.h>
  34 #include <stdlib.h>
  35 #include <dm/root.h>
  36 #include "../common/ge_common.h"
  37 #include "../common/vpd_reader.h"
  38 #include "../../../drivers/net/e1000.h"
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 static int confidx;  /* Default to generic. */
  42 static struct vpd_cache vpd;
  43
  44 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |      \
  45         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  46         PAD_CTL_HYS)
  47
  48 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  49         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  50         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  51
  52 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  53         PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  54
  55 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  56         PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  57
  58 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  59         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  60
  61 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  62         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  63         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  64
  65 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  66
  67 int dram_init(void)
  68 {
  69         gd->ram_size = imx_ddr_size();
  70
  71         return 0;
  72 }
  73
  74 static iomux_v3_cfg_t const uart3_pads[] = {
  75         MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  76         MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  77         MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  78         MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  79 };
  80
  81 static iomux_v3_cfg_t const uart4_pads[] = {
  82         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  83         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  84 };
  85
  86 static iomux_v3_cfg_t const enet_pads[] = {
  87         MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  88         MX6_PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
  89         MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  90         MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  91         MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  92         MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  93         MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  94         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  95         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  96         MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  97         MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  98         MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  99         MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 100         MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 101         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 102         /* AR8033 PHY Reset */
 103         MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
 104 };
 105
 106 static void setup_iomux_enet(void)
 107 {
 108         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 109
 110         /* Reset AR8033 PHY */
 111         gpio_request(IMX_GPIO_NR(1, 28), "fec_rst");
 112         gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
 113         mdelay(10);
 114         gpio_set_value(IMX_GPIO_NR(1, 28), 1);
 115         mdelay(1);
 116 }
 117
 118 static struct i2c_pads_info i2c_pad_info1 = {
 119         .scl = {
 120                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
 121                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
 122                 .gp = IMX_GPIO_NR(5, 27)
 123         },
 124         .sda = {
 125                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
 126                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
 127                 .gp = IMX_GPIO_NR(5, 26)
 128         }
 129 };
 130
 131 static struct i2c_pads_info i2c_pad_info2 = {
 132         .scl = {
 133                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
 134                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 135                 .gp = IMX_GPIO_NR(4, 12)
 136         },
 137         .sda = {
 138                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 139                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 140                 .gp = IMX_GPIO_NR(4, 13)
 141         }
 142 };
 143
 144 static struct i2c_pads_info i2c_pad_info3 = {
 145         .scl = {
 146                 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
 147                 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
 148                 .gp = IMX_GPIO_NR(1, 3)
 149         },
 150         .sda = {
 151                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
 152                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
 153                 .gp = IMX_GPIO_NR(1, 6)
 154         }
 155 };
 156
 157 static iomux_v3_cfg_t const pcie_pads[] = {
 158         MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 159         MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 160 };
 161
 162 static void setup_pcie(void)
 163 {
 164         imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
 165 }
 166
 167 static void setup_iomux_uart(void)
 168 {
 169         imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
 170         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 171 }
 172
 173 static int mx6_rgmii_rework(struct phy_device *phydev)
 174 {
 175         /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
 176         /* set device address 0x7 */
 177         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 178         /* offset 0x8016: CLK_25M Clock Select */
 179         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 180         /* enable register write, no post increment, address 0x7 */
 181         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 182         /* set to 125 MHz from local PLL source */
 183         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
 184
 185         /* rgmii tx clock delay enable */
 186         /* set debug port address: SerDes Test and System Mode Control */
 187         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 188         /* enable rgmii tx clock delay */
 189         /* set the reserved bits to avoid board specific voltage peak issue*/
 190         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
 191
 192         return 0;
 193 }
 194
 195 int board_phy_config(struct phy_device *phydev)
 196 {
 197         mx6_rgmii_rework(phydev);
 198
 199         if (phydev->drv->config)
 200                 phydev->drv->config(phydev);
 201
 202         return 0;
 203 }
 204
 205 #if defined(CONFIG_VIDEO_IPUV3)
 206 static iomux_v3_cfg_t const backlight_pads[] = {
 207         /* Power for LVDS Display */
 208         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 209 #define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
 210         /* Backlight enable for LVDS display */
 211         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 212 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
 213         /* backlight PWM brightness control */
 214         MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
 215 };
 216
 217 static void do_enable_hdmi(struct display_info_t const *dev)
 218 {
 219         imx_enable_hdmi_phy();
 220 }
 221
 222 static int is_b850v3(void)
 223 {
 224         return confidx == 3;
 225 }
 226
 227 static int detect_lcd(struct display_info_t const *dev)
 228 {
 229         return !is_b850v3();
 230 }
 231
 232 struct display_info_t const displays[] = {{
 233         .bus    = -1,
 234         .addr   = -1,
 235         .pixfmt = IPU_PIX_FMT_RGB24,
 236         .detect = detect_lcd,
 237         .enable = NULL,
 238         .mode   = {
 239                 .name           = "G121X1-L03",
 240                 .refresh        = 60,
 241                 .xres           = 1024,
 242                 .yres           = 768,
 243                 .pixclock       = 15385,
 244                 .left_margin    = 20,
 245                 .right_margin   = 300,
 246                 .upper_margin   = 30,
 247                 .lower_margin   = 8,
 248                 .hsync_len      = 1,
 249                 .vsync_len      = 1,
 250                 .sync           = FB_SYNC_EXT,
 251                 .vmode          = FB_VMODE_NONINTERLACED
 252 } }, {
 253         .bus    = -1,
 254         .addr   = 3,
 255         .pixfmt = IPU_PIX_FMT_RGB24,
 256         .detect = detect_hdmi,
 257         .enable = do_enable_hdmi,
 258         .mode   = {
 259                 .name           = "HDMI",
 260                 .refresh        = 60,
 261                 .xres           = 1024,
 262                 .yres           = 768,
 263                 .pixclock       = 15385,
 264                 .left_margin    = 220,
 265                 .right_margin   = 40,
 266                 .upper_margin   = 21,
 267                 .lower_margin   = 7,
 268                 .hsync_len      = 60,
 269                 .vsync_len      = 10,
 270                 .sync           = FB_SYNC_EXT,
 271                 .vmode          = FB_VMODE_NONINTERLACED
 272 } } };
 273 size_t display_count = ARRAY_SIZE(displays);
 274
 275 static void enable_videopll(void)
 276 {
 277         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 278         s32 timeout = 100000;
 279
 280         setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 281
 282         /* PLL_VIDEO  455MHz (24MHz * (37+11/12) / 2)
 283          *   |
 284          * PLL5
 285          *   |
 286          * CS2CDR[LDB_DI0_CLK_SEL]
 287          *   |
 288          *   +----> LDB_DI0_SERIAL_CLK_ROOT
 289          *   |
 290          *   +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU  455 / 7 = 65 MHz
 291          */
 292
 293         clrsetbits_le32(&ccm->analog_pll_video,
 294                         BM_ANADIG_PLL_VIDEO_DIV_SELECT |
 295                         BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
 296                         BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
 297                         BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
 298
 299         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 300         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 301
 302         clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 303
 304         while (timeout--)
 305                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 306                         break;
 307
 308         if (timeout < 0)
 309                 printf("Warning: video pll lock timeout!\n");
 310
 311         clrsetbits_le32(&ccm->analog_pll_video,
 312                         BM_ANADIG_PLL_VIDEO_BYPASS,
 313                         BM_ANADIG_PLL_VIDEO_ENABLE);
 314 }
 315
 316 static void setup_display_b850v3(void)
 317 {
 318         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 319         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 320
 321         enable_videopll();
 322
 323         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 324         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 325
 326         imx_setup_hdmi();
 327
 328         /* Set LDB_DI0 as clock source for IPU_DI0 */
 329         clrsetbits_le32(&mxc_ccm->chsccdr,
 330                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 331                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 332                          MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 333
 334         /* Turn on IPU LDB DI0 clocks */
 335         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 336
 337         enable_ipu_clock();
 338
 339         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 340                IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
 341                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 342                IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
 343                IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
 344                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 345                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 346                IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
 347                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
 348                IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
 349                &iomux->gpr[2]);
 350
 351         clrbits_le32(&iomux->gpr[3],
 352                      IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 353                      IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 354                      IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
 355 }
 356
 357 static void setup_display_bx50v3(void)
 358 {
 359         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 360         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 361
 362         enable_videopll();
 363
 364         /* When a reset/reboot is performed the display power needs to be turned
 365          * off for atleast 500ms. The boot time is ~300ms, we need to wait for
 366          * an additional 200ms here. Unfortunately we use external PMIC for
 367          * doing the reset, so can not differentiate between POR vs soft reset
 368          */
 369         mdelay(200);
 370
 371         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 372         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 373
 374         /* Set LDB_DI0 as clock source for IPU_DI0 */
 375         clrsetbits_le32(&mxc_ccm->chsccdr,
 376                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 377                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 378                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 379
 380         /* Turn on IPU LDB DI0 clocks */
 381         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 382
 383         enable_ipu_clock();
 384
 385         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 386                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 387                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 388                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 389                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
 390                &iomux->gpr[2]);
 391
 392         clrsetbits_le32(&iomux->gpr[3],
 393                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
 394                        (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 395                         IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
 396
 397         /* backlights off until needed */
 398         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 399                                          ARRAY_SIZE(backlight_pads));
 400         gpio_request(LVDS_POWER_GP, "lvds_power");
 401         gpio_direction_input(LVDS_POWER_GP);
 402 }
 403 #endif /* CONFIG_VIDEO_IPUV3 */
 404
 405 /*
 406  * Do not overwrite the console
 407  * Use always serial for U-Boot console
 408  */
 409 int overwrite_console(void)
 410 {
 411         return 1;
 412 }
 413
 414 #define VPD_TYPE_INVALID 0x00
 415 #define VPD_BLOCK_NETWORK 0x20
 416 #define VPD_BLOCK_HWID 0x44
 417 #define VPD_PRODUCT_B850 1
 418 #define VPD_PRODUCT_B650 2
 419 #define VPD_PRODUCT_B450 3
 420 #define VPD_HAS_MAC1 0x1
 421 #define VPD_HAS_MAC2 0x2
 422 #define VPD_MAC_ADDRESS_LENGTH 6
 423
 424 struct vpd_cache {
 425         bool is_read;
 426         u8 product_id;
 427         u8 has;
 428         unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
 429         unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
 430 };
 431
 432 /*
 433  * Extracts MAC and product information from the VPD.
 434  */
 435 static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
 436                         size_t size, u8 const *data)
 437 {
 438         if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
 439             size >= 1) {
 440                 vpd->product_id = data[0];
 441         } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
 442                    type != VPD_TYPE_INVALID) {
 443                 if (size >= 6) {
 444                         vpd->has |= VPD_HAS_MAC1;
 445                         memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
 446                 }
 447                 if (size >= 12) {
 448                         vpd->has |= VPD_HAS_MAC2;
 449                         memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
 450                 }
 451         }
 452
 453         return 0;
 454 }
 455
 456 static void process_vpd(struct vpd_cache *vpd)
 457 {
 458         int fec_index = -1;
 459         int i210_index = -1;
 460
 461         if (!vpd->is_read) {
 462                 printf("VPD wasn't read");
 463                 return;
 464         }
 465
 466         switch (vpd->product_id) {
 467         case VPD_PRODUCT_B450:
 468                 env_set("confidx", "1");
 469                 i210_index = 0;
 470                 fec_index = 1;
 471                 break;
 472         case VPD_PRODUCT_B650:
 473                 env_set("confidx", "2");
 474                 i210_index = 0;
 475                 fec_index = 1;
 476                 break;
 477         case VPD_PRODUCT_B850:
 478                 env_set("confidx", "3");
 479                 i210_index = 1;
 480                 fec_index = 2;
 481                 break;
 482         }
 483
 484         if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
 485                 eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
 486
 487         if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
 488                 eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
 489 }
 490
 491 int board_eth_init(bd_t *bis)
 492 {
 493         setup_iomux_enet();
 494         setup_pcie();
 495
 496         e1000_initialize(bis);
 497
 498         return cpu_eth_init(bis);
 499 }
 500
 501 static iomux_v3_cfg_t const misc_pads[] = {
 502         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(NO_PAD_CTRL),
 503         MX6_PAD_EIM_A25__GPIO5_IO02     | MUX_PAD_CTRL(NC_PAD_CTRL),
 504         MX6_PAD_EIM_CS0__GPIO2_IO23     | MUX_PAD_CTRL(NC_PAD_CTRL),
 505         MX6_PAD_EIM_CS1__GPIO2_IO24     | MUX_PAD_CTRL(NC_PAD_CTRL),
 506         MX6_PAD_EIM_OE__GPIO2_IO25      | MUX_PAD_CTRL(NC_PAD_CTRL),
 507         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(NC_PAD_CTRL),
 508         MX6_PAD_GPIO_1__GPIO1_IO01      | MUX_PAD_CTRL(NC_PAD_CTRL),
 509         MX6_PAD_GPIO_9__WDOG1_B         | MUX_PAD_CTRL(NC_PAD_CTRL),
 510 };
 511 #define SUS_S3_OUT      IMX_GPIO_NR(4, 11)
 512 #define WIFI_EN IMX_GPIO_NR(6, 14)
 513
 514 int board_early_init_f(void)
 515 {
 516         imx_iomux_v3_setup_multiple_pads(misc_pads,
 517                                          ARRAY_SIZE(misc_pads));
 518
 519         setup_iomux_uart();
 520
 521 #if defined(CONFIG_VIDEO_IPUV3)
 522         /* Set LDB clock to Video PLL */
 523         select_ldb_di_clock_source(MXC_PLL5_CLK);
 524 #endif
 525         return 0;
 526 }
 527
 528 static void set_confidx(const struct vpd_cache* vpd)
 529 {
 530         switch (vpd->product_id) {
 531         case VPD_PRODUCT_B450:
 532                 confidx = 1;
 533                 break;
 534         case VPD_PRODUCT_B650:
 535                 confidx = 2;
 536                 break;
 537         case VPD_PRODUCT_B850:
 538                 confidx = 3;
 539                 break;
 540         }
 541 }
 542
 543 int board_init(void)
 544 {
 545         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 546         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 547         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
 548
 549         if (!read_vpd(&vpd, vpd_callback)) {
 550                 int ret, rescan;
 551
 552                 vpd.is_read = true;
 553                 set_confidx(&vpd);
 554
 555                 ret = fdtdec_resetup(&rescan);
 556                 if (!ret && rescan) {
 557                         dm_uninit();
 558                         dm_init_and_scan(false);
 559                 }
 560         }
 561
 562         gpio_request(SUS_S3_OUT, "sus_s3_out");
 563         gpio_direction_output(SUS_S3_OUT, 1);
 564
 565         gpio_request(WIFI_EN, "wifi_en");
 566         gpio_direction_output(WIFI_EN, 1);
 567
 568 #if defined(CONFIG_VIDEO_IPUV3)
 569         if (is_b850v3())
 570                 setup_display_b850v3();
 571         else
 572                 setup_display_bx50v3();
 573
 574         gpio_request(LVDS_BACKLIGHT_GP, "lvds_backlight");
 575         gpio_direction_input(LVDS_BACKLIGHT_GP);
 576 #endif
 577
 578         /* address of boot parameters */
 579         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 580
 581         return 0;
 582 }
 583
 584 #ifdef CONFIG_CMD_BMODE
 585 static const struct boot_mode board_boot_modes[] = {
 586         /* 4 bit bus width */
 587         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 588         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 589         {NULL,   0},
 590 };
 591 #endif
 592
 593 void pmic_init(void)
 594 {
 595 #define I2C_PMIC                0x2
 596 #define DA9063_I2C_ADDR         0x58
 597 #define DA9063_REG_BCORE2_CFG   0x9D
 598 #define DA9063_REG_BCORE1_CFG   0x9E
 599 #define DA9063_REG_BPRO_CFG     0x9F
 600 #define DA9063_REG_BIO_CFG      0xA0
 601 #define DA9063_REG_BMEM_CFG     0xA1
 602 #define DA9063_REG_BPERI_CFG    0xA2
 603 #define DA9063_BUCK_MODE_MASK   0xC0
 604 #define DA9063_BUCK_MODE_MANUAL 0x00
 605 #define DA9063_BUCK_MODE_SLEEP  0x40
 606 #define DA9063_BUCK_MODE_SYNC   0x80
 607 #define DA9063_BUCK_MODE_AUTO   0xC0
 608
 609         uchar val;
 610
 611         i2c_set_bus_num(I2C_PMIC);
 612
 613         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
 614         val &= ~DA9063_BUCK_MODE_MASK;
 615         val |= DA9063_BUCK_MODE_SYNC;
 616         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
 617
 618         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
 619         val &= ~DA9063_BUCK_MODE_MASK;
 620         val |= DA9063_BUCK_MODE_SYNC;
 621         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
 622
 623         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
 624         val &= ~DA9063_BUCK_MODE_MASK;
 625         val |= DA9063_BUCK_MODE_SYNC;
 626         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
 627
 628         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
 629         val &= ~DA9063_BUCK_MODE_MASK;
 630         val |= DA9063_BUCK_MODE_SYNC;
 631         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
 632
 633         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
 634         val &= ~DA9063_BUCK_MODE_MASK;
 635         val |= DA9063_BUCK_MODE_SYNC;
 636         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
 637
 638         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
 639         val &= ~DA9063_BUCK_MODE_MASK;
 640         val |= DA9063_BUCK_MODE_SYNC;
 641         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
 642 }
 643
 644 int board_late_init(void)
 645 {
 646         process_vpd(&vpd);
 647
 648 #ifdef CONFIG_CMD_BMODE
 649         add_board_boot_modes(board_boot_modes);
 650 #endif
 651
 652         if (is_b850v3())
 653                 env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
 654         else
 655                 env_set("videoargs", "video=LVDS-1:1024x768@65");
 656
 657         /* board specific pmic init */
 658         pmic_init();
 659
 660         check_time();
 661
 662         return 0;
 663 }
 664
 665 /*
 666  * Removes the 'eth[0-9]*addr' environment variable with the given index
 667  *
 668  * @param index [in] the index of the eth_device whose variable is to be removed
 669  */
 670 static void remove_ethaddr_env_var(int index)
 671 {
 672         char env_var_name[9];
 673
 674         sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
 675         env_set(env_var_name, NULL);
 676 }
 677
 678 int last_stage_init(void)
 679 {
 680         int i;
 681
 682         /*
 683          * Remove first three ethaddr which may have been created by
 684          * function process_vpd().
 685          */
 686         for (i = 0; i < 3; ++i)
 687                 remove_ethaddr_env_var(i);
 688
 689         return 0;
 690 }
 691
 692 int checkboard(void)
 693 {
 694         printf("BOARD: %s\n", CONFIG_BOARD_NAME);
 695         return 0;
 696 }
 697
 698 #ifdef CONFIG_OF_BOARD_SETUP
 699 int ft_board_setup(void *blob, bd_t *bd)
 700 {
 701         fdt_setprop(blob, 0, "ge,boot-ver", version_string,
 702                                             strlen(version_string) + 1);
 703         return 0;
 704 }
 705 #endif
 706
 707 static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 708 {
 709 #if CONFIG_IS_ENABLED(DM_VIDEO)
 710         int ret;
 711         struct udevice *dev;
 712
 713 #ifdef CONFIG_VIDEO_IPUV3
 714         if (!is_b850v3()) {
 715                 gpio_direction_output(LVDS_POWER_GP, 1);
 716
 717                 /* We need at least 200ms between power on and backlight on
 718                  * as per specifications from CHI MEI
 719                  */
 720                 mdelay(250);
 721
 722                 /* enable backlight PWM 1 */
 723                 pwm_init(0, 0, 0);
 724
 725                 /* duty cycle 5000000ns, period: 5000000ns */
 726                 pwm_config(0, 5000000, 5000000);
 727
 728                 /* Backlight Power */
 729                 gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 730
 731                 pwm_enable(0);
 732         }
 733 #endif
 734
 735         /* Probe, to find a video device to be used to show a message on
 736          * the vidconsole.
 737          */
 738         ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
 739         if (ret)
 740                 return ret;
 741 #endif
 742
 743         return 0;
 744 }
 745
 746 U_BOOT_CMD(
 747        bx50_backlight_enable, 1,      1,      do_backlight_enable,
 748        "enable Bx50 backlight",
 749        ""
 750 );
 751
 752 int board_fit_config_name_match(const char *name)
 753 {
 754         if (!vpd.is_read)
 755                 return strcmp(name, "imx6q-bx50v3");
 756
 757         switch (vpd.product_id) {
 758         case VPD_PRODUCT_B450:
 759                 return strcmp(name, "imx6q-b450v3");
 760         case VPD_PRODUCT_B650:
 761                 return strcmp(name, "imx6q-b650v3");
 762         case VPD_PRODUCT_B850:
 763                 return strcmp(name, "imx6q-b850v3");
 764         default:
 765                 return -1;
 766         }
 767 }
 768
 769 int embedded_dtb_select(void)
 770 {
 771         vpd.is_read = false;
 772         return fdtdec_setup();
 773 }