1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015 Timesys Corporation
4 * Copyright 2015 General Electric Company
5 * Copyright 2012 Freescale Semiconductor, Inc.
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/mx6-pins.h>
14 #include <linux/errno.h>
15 #include <linux/libfdt.h>
17 #include <asm/mach-imx/mxc_i2c.h>
18 #include <asm/mach-imx/iomux-v3.h>
19 #include <asm/mach-imx/boot_mode.h>
20 #include <asm/mach-imx/video.h>
22 #include <fsl_esdhc_imx.h>
26 #include <asm/arch/mxc_hdmi.h>
27 #include <asm/arch/crm_regs.h>
29 #include <asm/arch/sys_proto.h>
36 #include "../common/ge_common.h"
37 #include "../common/vpd_reader.h"
38 #include "../../../drivers/net/e1000.h"
41 DECLARE_GLOBAL_DATA_PTR;
43 static int confidx; /* Default to generic. */
44 static struct vpd_cache vpd;
46 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
47 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
50 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
51 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
52 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
54 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
55 PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
57 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
58 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
60 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
61 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
63 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
64 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
65 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
67 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
71 gd->ram_size = imx_ddr_size();
76 static iomux_v3_cfg_t const uart3_pads[] = {
77 MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
78 MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
79 MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
80 MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
83 static iomux_v3_cfg_t const uart4_pads[] = {
84 MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
85 MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
88 static struct i2c_pads_info i2c_pad_info1 = {
90 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
91 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
92 .gp = IMX_GPIO_NR(5, 27)
95 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
96 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
97 .gp = IMX_GPIO_NR(5, 26)
101 static struct i2c_pads_info i2c_pad_info2 = {
103 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
104 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
105 .gp = IMX_GPIO_NR(4, 12)
108 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
109 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
110 .gp = IMX_GPIO_NR(4, 13)
114 static struct i2c_pads_info i2c_pad_info3 = {
116 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
117 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
118 .gp = IMX_GPIO_NR(1, 3)
121 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
122 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
123 .gp = IMX_GPIO_NR(1, 6)
127 static void setup_iomux_uart(void)
129 imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
130 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
133 static int mx6_rgmii_rework(struct phy_device *phydev)
135 /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
136 /* set device address 0x7 */
137 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
138 /* offset 0x8016: CLK_25M Clock Select */
139 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
140 /* enable register write, no post increment, address 0x7 */
141 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
142 /* set to 125 MHz from local PLL source */
143 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
145 /* rgmii tx clock delay enable */
146 /* set debug port address: SerDes Test and System Mode Control */
147 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
148 /* enable rgmii tx clock delay */
149 /* set the reserved bits to avoid board specific voltage peak issue*/
150 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
155 int board_phy_config(struct phy_device *phydev)
157 mx6_rgmii_rework(phydev);
159 if (phydev->drv->config)
160 phydev->drv->config(phydev);
165 #if defined(CONFIG_VIDEO_IPUV3)
166 static iomux_v3_cfg_t const backlight_pads[] = {
167 /* Power for LVDS Display */
168 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
169 #define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
170 /* Backlight enable for LVDS display */
171 MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
172 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
173 /* backlight PWM brightness control */
174 MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
177 static void do_enable_hdmi(struct display_info_t const *dev)
179 imx_enable_hdmi_phy();
182 static int is_b850v3(void)
187 static int detect_lcd(struct display_info_t const *dev)
192 struct display_info_t const displays[] = {{
195 .pixfmt = IPU_PIX_FMT_RGB24,
196 .detect = detect_lcd,
199 .name = "G121X1-L03",
211 .vmode = FB_VMODE_NONINTERLACED
215 .pixfmt = IPU_PIX_FMT_RGB24,
216 .detect = detect_hdmi,
217 .enable = do_enable_hdmi,
231 .vmode = FB_VMODE_NONINTERLACED
233 size_t display_count = ARRAY_SIZE(displays);
235 static void enable_videopll(void)
237 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
238 s32 timeout = 100000;
240 setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
242 /* PLL_VIDEO 455MHz (24MHz * (37+11/12) / 2)
246 * CS2CDR[LDB_DI0_CLK_SEL]
248 * +----> LDB_DI0_SERIAL_CLK_ROOT
250 * +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU 455 / 7 = 65 MHz
253 clrsetbits_le32(&ccm->analog_pll_video,
254 BM_ANADIG_PLL_VIDEO_DIV_SELECT |
255 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
256 BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
257 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
259 writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
260 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
262 clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
265 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
269 printf("Warning: video pll lock timeout!\n");
271 clrsetbits_le32(&ccm->analog_pll_video,
272 BM_ANADIG_PLL_VIDEO_BYPASS,
273 BM_ANADIG_PLL_VIDEO_ENABLE);
276 static void setup_display_b850v3(void)
278 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
279 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
283 /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
284 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
288 /* Set LDB_DI0 as clock source for IPU_DI0 */
289 clrsetbits_le32(&mxc_ccm->chsccdr,
290 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
291 (CHSCCDR_CLK_SEL_LDB_DI0 <<
292 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
294 /* Turn on IPU LDB DI0 clocks */
295 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
299 writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
300 IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
301 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
302 IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
303 IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
304 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
305 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
306 IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
307 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
308 IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
311 clrbits_le32(&iomux->gpr[3],
312 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
313 IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
314 IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
317 static void setup_display_bx50v3(void)
319 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
320 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
324 /* When a reset/reboot is performed the display power needs to be turned
325 * off for atleast 500ms. The boot time is ~300ms, we need to wait for
326 * an additional 200ms here. Unfortunately we use external PMIC for
327 * doing the reset, so can not differentiate between POR vs soft reset
331 /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
332 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
334 /* Set LDB_DI0 as clock source for IPU_DI0 */
335 clrsetbits_le32(&mxc_ccm->chsccdr,
336 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
337 (CHSCCDR_CLK_SEL_LDB_DI0 <<
338 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
340 /* Turn on IPU LDB DI0 clocks */
341 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
345 writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
346 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
347 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
348 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
349 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
352 clrsetbits_le32(&iomux->gpr[3],
353 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
354 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
355 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
357 /* backlights off until needed */
358 imx_iomux_v3_setup_multiple_pads(backlight_pads,
359 ARRAY_SIZE(backlight_pads));
360 gpio_request(LVDS_POWER_GP, "lvds_power");
361 gpio_direction_input(LVDS_POWER_GP);
363 #endif /* CONFIG_VIDEO_IPUV3 */
366 * Do not overwrite the console
367 * Use always serial for U-Boot console
369 int overwrite_console(void)
374 #define VPD_TYPE_INVALID 0x00
375 #define VPD_BLOCK_NETWORK 0x20
376 #define VPD_BLOCK_HWID 0x44
377 #define VPD_PRODUCT_B850 1
378 #define VPD_PRODUCT_B650 2
379 #define VPD_PRODUCT_B450 3
380 #define VPD_HAS_MAC1 0x1
381 #define VPD_HAS_MAC2 0x2
382 #define VPD_MAC_ADDRESS_LENGTH 6
388 unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
389 unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
393 * Extracts MAC and product information from the VPD.
395 static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
396 size_t size, u8 const *data)
398 if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
400 vpd->product_id = data[0];
401 } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
402 type != VPD_TYPE_INVALID) {
404 vpd->has |= VPD_HAS_MAC1;
405 memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
408 vpd->has |= VPD_HAS_MAC2;
409 memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
416 static void process_vpd(struct vpd_cache *vpd)
422 printf("VPD wasn't read");
426 if (vpd->has & VPD_HAS_MAC1)
427 eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
429 env_set("ethact", "eth0");
431 switch (vpd->product_id) {
432 case VPD_PRODUCT_B450:
433 env_set("confidx", "1");
436 case VPD_PRODUCT_B650:
437 env_set("confidx", "2");
440 case VPD_PRODUCT_B850:
441 env_set("confidx", "3");
446 if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
447 eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
450 static iomux_v3_cfg_t const misc_pads[] = {
451 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
452 MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL),
453 MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL),
454 MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL),
455 MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL),
456 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL),
457 MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL),
458 MX6_PAD_GPIO_9__WDOG1_B | MUX_PAD_CTRL(NC_PAD_CTRL),
460 #define SUS_S3_OUT IMX_GPIO_NR(4, 11)
461 #define WIFI_EN IMX_GPIO_NR(6, 14)
463 int board_early_init_f(void)
465 imx_iomux_v3_setup_multiple_pads(misc_pads,
466 ARRAY_SIZE(misc_pads));
470 #if defined(CONFIG_VIDEO_IPUV3)
471 /* Set LDB clock to Video PLL */
472 select_ldb_di_clock_source(MXC_PLL5_CLK);
477 static void set_confidx(const struct vpd_cache* vpd)
479 switch (vpd->product_id) {
480 case VPD_PRODUCT_B450:
483 case VPD_PRODUCT_B650:
486 case VPD_PRODUCT_B850:
494 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
495 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
496 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
498 if (!read_vpd(&vpd, vpd_callback)) {
504 ret = fdtdec_resetup(&rescan);
505 if (!ret && rescan) {
507 dm_init_and_scan(false);
511 gpio_request(SUS_S3_OUT, "sus_s3_out");
512 gpio_direction_output(SUS_S3_OUT, 1);
514 gpio_request(WIFI_EN, "wifi_en");
515 gpio_direction_output(WIFI_EN, 1);
517 #if defined(CONFIG_VIDEO_IPUV3)
519 setup_display_b850v3();
521 setup_display_bx50v3();
523 gpio_request(LVDS_BACKLIGHT_GP, "lvds_backlight");
524 gpio_direction_input(LVDS_BACKLIGHT_GP);
527 /* address of boot parameters */
528 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
533 #ifdef CONFIG_CMD_BMODE
534 static const struct boot_mode board_boot_modes[] = {
535 /* 4 bit bus width */
536 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
537 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
545 #define DA9063_I2C_ADDR 0x58
546 #define DA9063_REG_BCORE2_CFG 0x9D
547 #define DA9063_REG_BCORE1_CFG 0x9E
548 #define DA9063_REG_BPRO_CFG 0x9F
549 #define DA9063_REG_BIO_CFG 0xA0
550 #define DA9063_REG_BMEM_CFG 0xA1
551 #define DA9063_REG_BPERI_CFG 0xA2
552 #define DA9063_BUCK_MODE_MASK 0xC0
553 #define DA9063_BUCK_MODE_MANUAL 0x00
554 #define DA9063_BUCK_MODE_SLEEP 0x40
555 #define DA9063_BUCK_MODE_SYNC 0x80
556 #define DA9063_BUCK_MODE_AUTO 0xC0
560 i2c_set_bus_num(I2C_PMIC);
562 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
563 val &= ~DA9063_BUCK_MODE_MASK;
564 val |= DA9063_BUCK_MODE_SYNC;
565 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
567 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
568 val &= ~DA9063_BUCK_MODE_MASK;
569 val |= DA9063_BUCK_MODE_SYNC;
570 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
572 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
573 val &= ~DA9063_BUCK_MODE_MASK;
574 val |= DA9063_BUCK_MODE_SYNC;
575 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
577 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
578 val &= ~DA9063_BUCK_MODE_MASK;
579 val |= DA9063_BUCK_MODE_SYNC;
580 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
582 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
583 val &= ~DA9063_BUCK_MODE_MASK;
584 val |= DA9063_BUCK_MODE_SYNC;
585 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
587 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
588 val &= ~DA9063_BUCK_MODE_MASK;
589 val |= DA9063_BUCK_MODE_SYNC;
590 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
593 int board_late_init(void)
597 #ifdef CONFIG_CMD_BMODE
598 add_board_boot_modes(board_boot_modes);
602 env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
604 env_set("videoargs", "video=LVDS-1:1024x768@65");
606 /* board specific pmic init */
617 * Removes the 'eth[0-9]*addr' environment variable with the given index
619 * @param index [in] the index of the eth_device whose variable is to be removed
621 static void remove_ethaddr_env_var(int index)
623 char env_var_name[9];
625 sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
626 env_set(env_var_name, NULL);
629 int last_stage_init(void)
634 * Remove first three ethaddr which may have been created by
635 * function process_vpd().
637 for (i = 0; i < 3; ++i)
638 remove_ethaddr_env_var(i);
645 printf("BOARD: %s\n", CONFIG_BOARD_NAME);
649 #ifdef CONFIG_OF_BOARD_SETUP
650 int ft_board_setup(void *blob, bd_t *bd)
652 char *rtc_status = env_get("rtc_status");
654 fdt_setprop(blob, 0, "ge,boot-ver", version_string,
655 strlen(version_string) + 1);
657 fdt_setprop(blob, 0, "ge,rtc-status", rtc_status,
658 strlen(rtc_status) + 1);
663 static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
665 #if CONFIG_IS_ENABLED(DM_VIDEO)
669 #ifdef CONFIG_VIDEO_IPUV3
671 gpio_direction_output(LVDS_POWER_GP, 1);
673 /* We need at least 200ms between power on and backlight on
674 * as per specifications from CHI MEI
678 /* enable backlight PWM 1 */
681 /* duty cycle 5000000ns, period: 5000000ns */
682 pwm_config(0, 5000000, 5000000);
684 /* Backlight Power */
685 gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
691 /* Probe, to find a video device to be used to show a message on
694 ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
703 bx50_backlight_enable, 1, 1, do_backlight_enable,
704 "enable Bx50 backlight",
708 int board_fit_config_name_match(const char *name)
711 return strcmp(name, "imx6q-bx50v3");
713 switch (vpd.product_id) {
714 case VPD_PRODUCT_B450:
715 return strcmp(name, "imx6q-b450v3");
716 case VPD_PRODUCT_B650:
717 return strcmp(name, "imx6q-b650v3");
718 case VPD_PRODUCT_B850:
719 return strcmp(name, "imx6q-b850v3");
725 int embedded_dtb_select(void)
728 return fdtdec_setup();