board/ge/bx50v3/bx50v3.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Timesys Corporation
   4  * Copyright 2015 General Electric Company
   5  * Copyright 2012 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <init.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <env.h>
  14 #include <linux/errno.h>
  15 #include <linux/libfdt.h>
  16 #include <asm/gpio.h>
  17 #include <asm/mach-imx/mxc_i2c.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/mach-imx/boot_mode.h>
  20 #include <asm/mach-imx/video.h>
  21 #include <mmc.h>
  22 #include <fsl_esdhc_imx.h>
  23 #include <miiphy.h>
  24 #include <net.h>
  25 #include <netdev.h>
  26 #include <asm/arch/mxc_hdmi.h>
  27 #include <asm/arch/crm_regs.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/sys_proto.h>
  30 #include <i2c.h>
  31 #include <input.h>
  32 #include <pwm.h>
  33 #include <version.h>
  34 #include <stdlib.h>
  35 #include <dm/root.h>
  36 #include "../common/ge_common.h"
  37 #include "../common/vpd_reader.h"
  38 #include "../../../drivers/net/e1000.h"
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 static int confidx;  /* Default to generic. */
  42 static struct vpd_cache vpd;
  43
  44 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |      \
  45         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  46         PAD_CTL_HYS)
  47
  48 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  49         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  50         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  51
  52 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  53         PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  54
  55 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  56         PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  57
  58 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  59         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  60
  61 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  62         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  63         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  64
  65 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  66
  67 int dram_init(void)
  68 {
  69         gd->ram_size = imx_ddr_size();
  70
  71         return 0;
  72 }
  73
  74 static iomux_v3_cfg_t const uart3_pads[] = {
  75         MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  76         MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  77         MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  78         MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  79 };
  80
  81 static iomux_v3_cfg_t const uart4_pads[] = {
  82         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  83         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  84 };
  85
  86 static iomux_v3_cfg_t const enet_pads[] = {
  87         MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  88         MX6_PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
  89         MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  90         MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  91         MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  92         MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  93         MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  94         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  95         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  96         MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  97         MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  98         MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  99         MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 100         MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 101         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 102         /* AR8033 PHY Reset */
 103         MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
 104 };
 105
 106 static void setup_iomux_enet(void)
 107 {
 108         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 109
 110         /* Reset AR8033 PHY */
 111         gpio_request(IMX_GPIO_NR(1, 28), "fec_rst");
 112         gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
 113         mdelay(10);
 114         gpio_set_value(IMX_GPIO_NR(1, 28), 1);
 115         mdelay(1);
 116 }
 117
 118 static struct i2c_pads_info i2c_pad_info1 = {
 119         .scl = {
 120                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
 121                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
 122                 .gp = IMX_GPIO_NR(5, 27)
 123         },
 124         .sda = {
 125                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
 126                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
 127                 .gp = IMX_GPIO_NR(5, 26)
 128         }
 129 };
 130
 131 static struct i2c_pads_info i2c_pad_info2 = {
 132         .scl = {
 133                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
 134                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 135                 .gp = IMX_GPIO_NR(4, 12)
 136         },
 137         .sda = {
 138                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 139                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 140                 .gp = IMX_GPIO_NR(4, 13)
 141         }
 142 };
 143
 144 static struct i2c_pads_info i2c_pad_info3 = {
 145         .scl = {
 146                 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
 147                 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
 148                 .gp = IMX_GPIO_NR(1, 3)
 149         },
 150         .sda = {
 151                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
 152                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
 153                 .gp = IMX_GPIO_NR(1, 6)
 154         }
 155 };
 156
 157 static iomux_v3_cfg_t const pcie_pads[] = {
 158         MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 159         MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 160 };
 161
 162 static void setup_pcie(void)
 163 {
 164         imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
 165 }
 166
 167 static void setup_iomux_uart(void)
 168 {
 169         imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
 170         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 171 }
 172
 173 static int mx6_rgmii_rework(struct phy_device *phydev)
 174 {
 175         /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
 176         /* set device address 0x7 */
 177         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 178         /* offset 0x8016: CLK_25M Clock Select */
 179         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 180         /* enable register write, no post increment, address 0x7 */
 181         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 182         /* set to 125 MHz from local PLL source */
 183         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
 184
 185         /* rgmii tx clock delay enable */
 186         /* set debug port address: SerDes Test and System Mode Control */
 187         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 188         /* enable rgmii tx clock delay */
 189         /* set the reserved bits to avoid board specific voltage peak issue*/
 190         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
 191
 192         return 0;
 193 }
 194
 195 int board_phy_config(struct phy_device *phydev)
 196 {
 197         mx6_rgmii_rework(phydev);
 198
 199         if (phydev->drv->config)
 200                 phydev->drv->config(phydev);
 201
 202         return 0;
 203 }
 204
 205 #if defined(CONFIG_VIDEO_IPUV3)
 206 static iomux_v3_cfg_t const backlight_pads[] = {
 207         /* Power for LVDS Display */
 208         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 209 #define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
 210         /* Backlight enable for LVDS display */
 211         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 212 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
 213         /* backlight PWM brightness control */
 214         MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
 215 };
 216
 217 static void do_enable_hdmi(struct display_info_t const *dev)
 218 {
 219         imx_enable_hdmi_phy();
 220 }
 221
 222 int board_cfb_skip(void)
 223 {
 224         gpio_direction_output(LVDS_POWER_GP, 1);
 225
 226         return 0;
 227 }
 228
 229 static int is_b850v3(void)
 230 {
 231         return confidx == 3;
 232 }
 233
 234 static int detect_lcd(struct display_info_t const *dev)
 235 {
 236         return !is_b850v3();
 237 }
 238
 239 struct display_info_t const displays[] = {{
 240         .bus    = -1,
 241         .addr   = -1,
 242         .pixfmt = IPU_PIX_FMT_RGB24,
 243         .detect = detect_lcd,
 244         .enable = NULL,
 245         .mode   = {
 246                 .name           = "G121X1-L03",
 247                 .refresh        = 60,
 248                 .xres           = 1024,
 249                 .yres           = 768,
 250                 .pixclock       = 15385,
 251                 .left_margin    = 20,
 252                 .right_margin   = 300,
 253                 .upper_margin   = 30,
 254                 .lower_margin   = 8,
 255                 .hsync_len      = 1,
 256                 .vsync_len      = 1,
 257                 .sync           = FB_SYNC_EXT,
 258                 .vmode          = FB_VMODE_NONINTERLACED
 259 } }, {
 260         .bus    = -1,
 261         .addr   = 3,
 262         .pixfmt = IPU_PIX_FMT_RGB24,
 263         .detect = detect_hdmi,
 264         .enable = do_enable_hdmi,
 265         .mode   = {
 266                 .name           = "HDMI",
 267                 .refresh        = 60,
 268                 .xres           = 1024,
 269                 .yres           = 768,
 270                 .pixclock       = 15385,
 271                 .left_margin    = 220,
 272                 .right_margin   = 40,
 273                 .upper_margin   = 21,
 274                 .lower_margin   = 7,
 275                 .hsync_len      = 60,
 276                 .vsync_len      = 10,
 277                 .sync           = FB_SYNC_EXT,
 278                 .vmode          = FB_VMODE_NONINTERLACED
 279 } } };
 280 size_t display_count = ARRAY_SIZE(displays);
 281
 282 static void enable_videopll(void)
 283 {
 284         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 285         s32 timeout = 100000;
 286
 287         setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 288
 289         /* PLL_VIDEO  455MHz (24MHz * (37+11/12) / 2)
 290          *   |
 291          * PLL5
 292          *   |
 293          * CS2CDR[LDB_DI0_CLK_SEL]
 294          *   |
 295          *   +----> LDB_DI0_SERIAL_CLK_ROOT
 296          *   |
 297          *   +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU  455 / 7 = 65 MHz
 298          */
 299
 300         clrsetbits_le32(&ccm->analog_pll_video,
 301                         BM_ANADIG_PLL_VIDEO_DIV_SELECT |
 302                         BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
 303                         BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
 304                         BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
 305
 306         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 307         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 308
 309         clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 310
 311         while (timeout--)
 312                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 313                         break;
 314
 315         if (timeout < 0)
 316                 printf("Warning: video pll lock timeout!\n");
 317
 318         clrsetbits_le32(&ccm->analog_pll_video,
 319                         BM_ANADIG_PLL_VIDEO_BYPASS,
 320                         BM_ANADIG_PLL_VIDEO_ENABLE);
 321 }
 322
 323 static void setup_display_b850v3(void)
 324 {
 325         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 326         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 327
 328         enable_videopll();
 329
 330         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 331         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 332
 333         imx_setup_hdmi();
 334
 335         /* Set LDB_DI0 as clock source for IPU_DI0 */
 336         clrsetbits_le32(&mxc_ccm->chsccdr,
 337                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 338                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 339                          MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 340
 341         /* Turn on IPU LDB DI0 clocks */
 342         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 343
 344         enable_ipu_clock();
 345
 346         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 347                IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
 348                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 349                IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
 350                IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
 351                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 352                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 353                IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
 354                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
 355                IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
 356                &iomux->gpr[2]);
 357
 358         clrbits_le32(&iomux->gpr[3],
 359                      IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 360                      IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 361                      IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
 362 }
 363
 364 static void setup_display_bx50v3(void)
 365 {
 366         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 367         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 368
 369         enable_videopll();
 370
 371         /* When a reset/reboot is performed the display power needs to be turned
 372          * off for atleast 500ms. The boot time is ~300ms, we need to wait for
 373          * an additional 200ms here. Unfortunately we use external PMIC for
 374          * doing the reset, so can not differentiate between POR vs soft reset
 375          */
 376         mdelay(200);
 377
 378         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 379         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 380
 381         /* Set LDB_DI0 as clock source for IPU_DI0 */
 382         clrsetbits_le32(&mxc_ccm->chsccdr,
 383                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 384                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 385                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 386
 387         /* Turn on IPU LDB DI0 clocks */
 388         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 389
 390         enable_ipu_clock();
 391
 392         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 393                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 394                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 395                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 396                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
 397                &iomux->gpr[2]);
 398
 399         clrsetbits_le32(&iomux->gpr[3],
 400                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
 401                        (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 402                         IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
 403
 404         /* backlights off until needed */
 405         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 406                                          ARRAY_SIZE(backlight_pads));
 407         gpio_request(LVDS_POWER_GP, "lvds_power");
 408         gpio_direction_input(LVDS_POWER_GP);
 409 }
 410 #endif /* CONFIG_VIDEO_IPUV3 */
 411
 412 /*
 413  * Do not overwrite the console
 414  * Use always serial for U-Boot console
 415  */
 416 int overwrite_console(void)
 417 {
 418         return 1;
 419 }
 420
 421 #define VPD_TYPE_INVALID 0x00
 422 #define VPD_BLOCK_NETWORK 0x20
 423 #define VPD_BLOCK_HWID 0x44
 424 #define VPD_PRODUCT_B850 1
 425 #define VPD_PRODUCT_B650 2
 426 #define VPD_PRODUCT_B450 3
 427 #define VPD_HAS_MAC1 0x1
 428 #define VPD_HAS_MAC2 0x2
 429 #define VPD_MAC_ADDRESS_LENGTH 6
 430
 431 struct vpd_cache {
 432         bool is_read;
 433         u8 product_id;
 434         u8 has;
 435         unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
 436         unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
 437 };
 438
 439 /*
 440  * Extracts MAC and product information from the VPD.
 441  */
 442 static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
 443                         size_t size, u8 const *data)
 444 {
 445         if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
 446             size >= 1) {
 447                 vpd->product_id = data[0];
 448         } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
 449                    type != VPD_TYPE_INVALID) {
 450                 if (size >= 6) {
 451                         vpd->has |= VPD_HAS_MAC1;
 452                         memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
 453                 }
 454                 if (size >= 12) {
 455                         vpd->has |= VPD_HAS_MAC2;
 456                         memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
 457                 }
 458         }
 459
 460         return 0;
 461 }
 462
 463 static void process_vpd(struct vpd_cache *vpd)
 464 {
 465         int fec_index = -1;
 466         int i210_index = -1;
 467
 468         if (!vpd->is_read) {
 469                 printf("VPD wasn't read");
 470                 return;
 471         }
 472
 473         switch (vpd->product_id) {
 474         case VPD_PRODUCT_B450:
 475                 env_set("confidx", "1");
 476                 i210_index = 0;
 477                 fec_index = 1;
 478                 break;
 479         case VPD_PRODUCT_B650:
 480                 env_set("confidx", "2");
 481                 i210_index = 0;
 482                 fec_index = 1;
 483                 break;
 484         case VPD_PRODUCT_B850:
 485                 env_set("confidx", "3");
 486                 i210_index = 1;
 487                 fec_index = 2;
 488                 break;
 489         }
 490
 491         if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
 492                 eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
 493
 494         if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
 495                 eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
 496 }
 497
 498 int board_eth_init(bd_t *bis)
 499 {
 500         setup_iomux_enet();
 501         setup_pcie();
 502
 503         e1000_initialize(bis);
 504
 505         return cpu_eth_init(bis);
 506 }
 507
 508 static iomux_v3_cfg_t const misc_pads[] = {
 509         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(NO_PAD_CTRL),
 510         MX6_PAD_EIM_A25__GPIO5_IO02     | MUX_PAD_CTRL(NC_PAD_CTRL),
 511         MX6_PAD_EIM_CS0__GPIO2_IO23     | MUX_PAD_CTRL(NC_PAD_CTRL),
 512         MX6_PAD_EIM_CS1__GPIO2_IO24     | MUX_PAD_CTRL(NC_PAD_CTRL),
 513         MX6_PAD_EIM_OE__GPIO2_IO25      | MUX_PAD_CTRL(NC_PAD_CTRL),
 514         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(NC_PAD_CTRL),
 515         MX6_PAD_GPIO_1__GPIO1_IO01      | MUX_PAD_CTRL(NC_PAD_CTRL),
 516         MX6_PAD_GPIO_9__WDOG1_B         | MUX_PAD_CTRL(NC_PAD_CTRL),
 517 };
 518 #define SUS_S3_OUT      IMX_GPIO_NR(4, 11)
 519 #define WIFI_EN IMX_GPIO_NR(6, 14)
 520
 521 int board_early_init_f(void)
 522 {
 523         imx_iomux_v3_setup_multiple_pads(misc_pads,
 524                                          ARRAY_SIZE(misc_pads));
 525
 526         setup_iomux_uart();
 527
 528 #if defined(CONFIG_VIDEO_IPUV3)
 529         /* Set LDB clock to Video PLL */
 530         select_ldb_di_clock_source(MXC_PLL5_CLK);
 531 #endif
 532         return 0;
 533 }
 534
 535 static void set_confidx(const struct vpd_cache* vpd)
 536 {
 537         switch (vpd->product_id) {
 538         case VPD_PRODUCT_B450:
 539                 confidx = 1;
 540                 break;
 541         case VPD_PRODUCT_B650:
 542                 confidx = 2;
 543                 break;
 544         case VPD_PRODUCT_B850:
 545                 confidx = 3;
 546                 break;
 547         }
 548 }
 549
 550 int board_init(void)
 551 {
 552         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 553         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 554         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
 555
 556         if (!read_vpd(&vpd, vpd_callback)) {
 557                 int ret, rescan;
 558
 559                 vpd.is_read = true;
 560                 set_confidx(&vpd);
 561
 562                 ret = fdtdec_resetup(&rescan);
 563                 if (!ret && rescan) {
 564                         dm_uninit();
 565                         dm_init_and_scan(false);
 566                 }
 567         }
 568
 569         gpio_request(SUS_S3_OUT, "sus_s3_out");
 570         gpio_direction_output(SUS_S3_OUT, 1);
 571
 572         gpio_request(WIFI_EN, "wifi_en");
 573         gpio_direction_output(WIFI_EN, 1);
 574
 575 #if defined(CONFIG_VIDEO_IPUV3)
 576         if (is_b850v3())
 577                 setup_display_b850v3();
 578         else
 579                 setup_display_bx50v3();
 580
 581         gpio_request(LVDS_BACKLIGHT_GP, "lvds_backlight");
 582         gpio_direction_input(LVDS_BACKLIGHT_GP);
 583 #endif
 584
 585         /* address of boot parameters */
 586         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 587
 588         return 0;
 589 }
 590
 591 #ifdef CONFIG_CMD_BMODE
 592 static const struct boot_mode board_boot_modes[] = {
 593         /* 4 bit bus width */
 594         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 595         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 596         {NULL,   0},
 597 };
 598 #endif
 599
 600 void pmic_init(void)
 601 {
 602 #define I2C_PMIC                0x2
 603 #define DA9063_I2C_ADDR         0x58
 604 #define DA9063_REG_BCORE2_CFG   0x9D
 605 #define DA9063_REG_BCORE1_CFG   0x9E
 606 #define DA9063_REG_BPRO_CFG     0x9F
 607 #define DA9063_REG_BIO_CFG      0xA0
 608 #define DA9063_REG_BMEM_CFG     0xA1
 609 #define DA9063_REG_BPERI_CFG    0xA2
 610 #define DA9063_BUCK_MODE_MASK   0xC0
 611 #define DA9063_BUCK_MODE_MANUAL 0x00
 612 #define DA9063_BUCK_MODE_SLEEP  0x40
 613 #define DA9063_BUCK_MODE_SYNC   0x80
 614 #define DA9063_BUCK_MODE_AUTO   0xC0
 615
 616         uchar val;
 617
 618         i2c_set_bus_num(I2C_PMIC);
 619
 620         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
 621         val &= ~DA9063_BUCK_MODE_MASK;
 622         val |= DA9063_BUCK_MODE_SYNC;
 623         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
 624
 625         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
 626         val &= ~DA9063_BUCK_MODE_MASK;
 627         val |= DA9063_BUCK_MODE_SYNC;
 628         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
 629
 630         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
 631         val &= ~DA9063_BUCK_MODE_MASK;
 632         val |= DA9063_BUCK_MODE_SYNC;
 633         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
 634
 635         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
 636         val &= ~DA9063_BUCK_MODE_MASK;
 637         val |= DA9063_BUCK_MODE_SYNC;
 638         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
 639
 640         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
 641         val &= ~DA9063_BUCK_MODE_MASK;
 642         val |= DA9063_BUCK_MODE_SYNC;
 643         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
 644
 645         i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
 646         val &= ~DA9063_BUCK_MODE_MASK;
 647         val |= DA9063_BUCK_MODE_SYNC;
 648         i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
 649 }
 650
 651 int board_late_init(void)
 652 {
 653         process_vpd(&vpd);
 654
 655 #ifdef CONFIG_CMD_BMODE
 656         add_board_boot_modes(board_boot_modes);
 657 #endif
 658
 659         if (is_b850v3())
 660                 env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
 661         else
 662                 env_set("videoargs", "video=LVDS-1:1024x768@65");
 663
 664         /* board specific pmic init */
 665         pmic_init();
 666
 667         check_time();
 668
 669         return 0;
 670 }
 671
 672 /*
 673  * Removes the 'eth[0-9]*addr' environment variable with the given index
 674  *
 675  * @param index [in] the index of the eth_device whose variable is to be removed
 676  */
 677 static void remove_ethaddr_env_var(int index)
 678 {
 679         char env_var_name[9];
 680
 681         sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
 682         env_set(env_var_name, NULL);
 683 }
 684
 685 int last_stage_init(void)
 686 {
 687         int i;
 688
 689         /*
 690          * Remove first three ethaddr which may have been created by
 691          * function process_vpd().
 692          */
 693         for (i = 0; i < 3; ++i)
 694                 remove_ethaddr_env_var(i);
 695
 696         return 0;
 697 }
 698
 699 int checkboard(void)
 700 {
 701         printf("BOARD: %s\n", CONFIG_BOARD_NAME);
 702         return 0;
 703 }
 704
 705 #ifdef CONFIG_OF_BOARD_SETUP
 706 int ft_board_setup(void *blob, bd_t *bd)
 707 {
 708         fdt_setprop(blob, 0, "ge,boot-ver", version_string,
 709                                             strlen(version_string) + 1);
 710         return 0;
 711 }
 712 #endif
 713
 714 static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 715 {
 716 #ifdef CONFIG_VIDEO_IPUV3
 717         /* We need at least 200ms between power on and backlight on
 718          * as per specifications from CHI MEI */
 719         mdelay(250);
 720
 721         /* enable backlight PWM 1 */
 722         pwm_init(0, 0, 0);
 723
 724         /* duty cycle 5000000ns, period: 5000000ns */
 725         pwm_config(0, 5000000, 5000000);
 726
 727         /* Backlight Power */
 728         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 729
 730         pwm_enable(0);
 731 #endif
 732
 733         return 0;
 734 }
 735
 736 U_BOOT_CMD(
 737        bx50_backlight_enable, 1,      1,      do_backlight_enable,
 738        "enable Bx50 backlight",
 739        ""
 740 );
 741
 742 int board_fit_config_name_match(const char *name)
 743 {
 744         if (!vpd.is_read)
 745                 return strcmp(name, "imx6q-bx50v3");
 746
 747         switch (vpd.product_id) {
 748         case VPD_PRODUCT_B450:
 749                 return strcmp(name, "imx6q-b450v3");
 750         case VPD_PRODUCT_B650:
 751                 return strcmp(name, "imx6q-b650v3");
 752         case VPD_PRODUCT_B850:
 753                 return strcmp(name, "imx6q-b850v3");
 754         default:
 755                 return -1;
 756         }
 757 }
 758
 759 int embedded_dtb_select(void)
 760 {
 761         vpd.is_read = false;
 762         return fdtdec_setup();
 763 }