board/ge/bx50v3/bx50v3.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Timesys Corporation
   4  * Copyright 2015 General Electric Company
   5  * Copyright 2012 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <init.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <env.h>
  14 #include <linux/errno.h>
  15 #include <linux/libfdt.h>
  16 #include <asm/gpio.h>
  17 #include <asm/mach-imx/iomux-v3.h>
  18 #include <asm/mach-imx/boot_mode.h>
  19 #include <asm/mach-imx/video.h>
  20 #include <mmc.h>
  21 #include <fsl_esdhc_imx.h>
  22 #include <miiphy.h>
  23 #include <net.h>
  24 #include <netdev.h>
  25 #include <asm/arch/mxc_hdmi.h>
  26 #include <asm/arch/crm_regs.h>
  27 #include <asm/io.h>
  28 #include <asm/arch/sys_proto.h>
  29 #include <power/regulator.h>
  30 #include <power/da9063_pmic.h>
  31 #include <input.h>
  32 #include <pwm.h>
  33 #include <version.h>
  34 #include <stdlib.h>
  35 #include <dm/root.h>
  36 #include "../common/ge_common.h"
  37 #include "../common/vpd_reader.h"
  38 #include "../../../drivers/net/e1000.h"
  39 #include <pci.h>
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 static int confidx;  /* Default to generic. */
  44 static struct vpd_cache vpd;
  45
  46 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |      \
  47         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  48         PAD_CTL_HYS)
  49
  50 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  51         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  52         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  53
  54 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  55         PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  56
  57 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  58         PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  59
  60 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  61         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  62
  63 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  64         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  65         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  66
  67 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  68
  69 int dram_init(void)
  70 {
  71         gd->ram_size = imx_ddr_size();
  72
  73         return 0;
  74 }
  75
  76 static iomux_v3_cfg_t const uart3_pads[] = {
  77         MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  78         MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  79         MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  80         MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  81 };
  82
  83 static iomux_v3_cfg_t const uart4_pads[] = {
  84         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  85         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  86 };
  87
  88 static void setup_iomux_uart(void)
  89 {
  90         imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
  91         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
  92 }
  93
  94 static int mx6_rgmii_rework(struct phy_device *phydev)
  95 {
  96         /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
  97         /* set device address 0x7 */
  98         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  99         /* offset 0x8016: CLK_25M Clock Select */
 100         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 101         /* enable register write, no post increment, address 0x7 */
 102         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 103         /* set to 125 MHz from local PLL source */
 104         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
 105
 106         /* rgmii tx clock delay enable */
 107         /* set debug port address: SerDes Test and System Mode Control */
 108         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 109         /* enable rgmii tx clock delay */
 110         /* set the reserved bits to avoid board specific voltage peak issue*/
 111         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
 112
 113         return 0;
 114 }
 115
 116 int board_phy_config(struct phy_device *phydev)
 117 {
 118         mx6_rgmii_rework(phydev);
 119
 120         if (phydev->drv->config)
 121                 phydev->drv->config(phydev);
 122
 123         return 0;
 124 }
 125
 126 #if defined(CONFIG_VIDEO_IPUV3)
 127 static iomux_v3_cfg_t const backlight_pads[] = {
 128         /* Power for LVDS Display */
 129         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 130 #define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
 131         /* Backlight enable for LVDS display */
 132         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 133 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
 134         /* backlight PWM brightness control */
 135         MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
 136 };
 137
 138 static void do_enable_hdmi(struct display_info_t const *dev)
 139 {
 140         imx_enable_hdmi_phy();
 141 }
 142
 143 static int is_b850v3(void)
 144 {
 145         return confidx == 3;
 146 }
 147
 148 static int detect_lcd(struct display_info_t const *dev)
 149 {
 150         return !is_b850v3();
 151 }
 152
 153 struct display_info_t const displays[] = {{
 154         .bus    = -1,
 155         .addr   = -1,
 156         .pixfmt = IPU_PIX_FMT_RGB24,
 157         .detect = detect_lcd,
 158         .enable = NULL,
 159         .mode   = {
 160                 .name           = "G121X1-L03",
 161                 .refresh        = 60,
 162                 .xres           = 1024,
 163                 .yres           = 768,
 164                 .pixclock       = 15385,
 165                 .left_margin    = 20,
 166                 .right_margin   = 300,
 167                 .upper_margin   = 30,
 168                 .lower_margin   = 8,
 169                 .hsync_len      = 1,
 170                 .vsync_len      = 1,
 171                 .sync           = FB_SYNC_EXT,
 172                 .vmode          = FB_VMODE_NONINTERLACED
 173 } }, {
 174         .bus    = -1,
 175         .addr   = 3,
 176         .pixfmt = IPU_PIX_FMT_RGB24,
 177         .detect = detect_hdmi,
 178         .enable = do_enable_hdmi,
 179         .mode   = {
 180                 .name           = "HDMI",
 181                 .refresh        = 60,
 182                 .xres           = 1024,
 183                 .yres           = 768,
 184                 .pixclock       = 15385,
 185                 .left_margin    = 220,
 186                 .right_margin   = 40,
 187                 .upper_margin   = 21,
 188                 .lower_margin   = 7,
 189                 .hsync_len      = 60,
 190                 .vsync_len      = 10,
 191                 .sync           = FB_SYNC_EXT,
 192                 .vmode          = FB_VMODE_NONINTERLACED
 193 } } };
 194 size_t display_count = ARRAY_SIZE(displays);
 195
 196 static void enable_videopll(void)
 197 {
 198         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 199         s32 timeout = 100000;
 200
 201         setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 202
 203         /* PLL_VIDEO  455MHz (24MHz * (37+11/12) / 2)
 204          *   |
 205          * PLL5
 206          *   |
 207          * CS2CDR[LDB_DI0_CLK_SEL]
 208          *   |
 209          *   +----> LDB_DI0_SERIAL_CLK_ROOT
 210          *   |
 211          *   +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU  455 / 7 = 65 MHz
 212          */
 213
 214         clrsetbits_le32(&ccm->analog_pll_video,
 215                         BM_ANADIG_PLL_VIDEO_DIV_SELECT |
 216                         BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
 217                         BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
 218                         BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
 219
 220         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 221         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 222
 223         clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 224
 225         while (timeout--)
 226                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 227                         break;
 228
 229         if (timeout < 0)
 230                 printf("Warning: video pll lock timeout!\n");
 231
 232         clrsetbits_le32(&ccm->analog_pll_video,
 233                         BM_ANADIG_PLL_VIDEO_BYPASS,
 234                         BM_ANADIG_PLL_VIDEO_ENABLE);
 235 }
 236
 237 static void setup_display_b850v3(void)
 238 {
 239         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 240         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 241
 242         enable_videopll();
 243
 244         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 245         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 246
 247         imx_setup_hdmi();
 248
 249         /* Set LDB_DI0 as clock source for IPU_DI0 */
 250         clrsetbits_le32(&mxc_ccm->chsccdr,
 251                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 252                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 253                          MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 254
 255         /* Turn on IPU LDB DI0 clocks */
 256         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 257
 258         enable_ipu_clock();
 259
 260         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 261                IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
 262                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 263                IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
 264                IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
 265                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 266                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 267                IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
 268                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
 269                IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
 270                &iomux->gpr[2]);
 271
 272         clrbits_le32(&iomux->gpr[3],
 273                      IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 274                      IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 275                      IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
 276 }
 277
 278 static void setup_display_bx50v3(void)
 279 {
 280         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 281         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 282
 283         enable_videopll();
 284
 285         /* When a reset/reboot is performed the display power needs to be turned
 286          * off for atleast 500ms. The boot time is ~300ms, we need to wait for
 287          * an additional 200ms here. Unfortunately we use external PMIC for
 288          * doing the reset, so can not differentiate between POR vs soft reset
 289          */
 290         mdelay(200);
 291
 292         /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
 293         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 294
 295         /* Set LDB_DI0 as clock source for IPU_DI0 */
 296         clrsetbits_le32(&mxc_ccm->chsccdr,
 297                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 298                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 299                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 300
 301         /* Turn on IPU LDB DI0 clocks */
 302         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 303
 304         enable_ipu_clock();
 305
 306         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 307                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 308                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 309                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 310                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
 311                &iomux->gpr[2]);
 312
 313         clrsetbits_le32(&iomux->gpr[3],
 314                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
 315                        (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 316                         IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
 317
 318         /* backlights off until needed */
 319         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 320                                          ARRAY_SIZE(backlight_pads));
 321         gpio_request(LVDS_POWER_GP, "lvds_power");
 322         gpio_direction_input(LVDS_POWER_GP);
 323 }
 324 #endif /* CONFIG_VIDEO_IPUV3 */
 325
 326 /*
 327  * Do not overwrite the console
 328  * Use always serial for U-Boot console
 329  */
 330 int overwrite_console(void)
 331 {
 332         return 1;
 333 }
 334
 335 #define VPD_TYPE_INVALID 0x00
 336 #define VPD_BLOCK_NETWORK 0x20
 337 #define VPD_BLOCK_HWID 0x44
 338 #define VPD_PRODUCT_B850 1
 339 #define VPD_PRODUCT_B650 2
 340 #define VPD_PRODUCT_B450 3
 341 #define VPD_HAS_MAC1 0x1
 342 #define VPD_HAS_MAC2 0x2
 343 #define VPD_MAC_ADDRESS_LENGTH 6
 344
 345 struct vpd_cache {
 346         bool is_read;
 347         u8 product_id;
 348         u8 has;
 349         unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
 350         unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
 351 };
 352
 353 /*
 354  * Extracts MAC and product information from the VPD.
 355  */
 356 static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
 357                         size_t size, u8 const *data)
 358 {
 359         if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
 360             size >= 1) {
 361                 vpd->product_id = data[0];
 362         } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
 363                    type != VPD_TYPE_INVALID) {
 364                 if (size >= 6) {
 365                         vpd->has |= VPD_HAS_MAC1;
 366                         memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
 367                 }
 368                 if (size >= 12) {
 369                         vpd->has |= VPD_HAS_MAC2;
 370                         memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
 371                 }
 372         }
 373
 374         return 0;
 375 }
 376
 377 static void process_vpd(struct vpd_cache *vpd)
 378 {
 379         int fec_index = 0;
 380         int i210_index = -1;
 381
 382         if (!vpd->is_read) {
 383                 printf("VPD wasn't read");
 384                 return;
 385         }
 386
 387         if (vpd->has & VPD_HAS_MAC1)
 388                 eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
 389
 390         env_set("ethact", "eth0");
 391
 392         switch (vpd->product_id) {
 393         case VPD_PRODUCT_B450:
 394                 env_set("confidx", "1");
 395                 i210_index = 1;
 396                 break;
 397         case VPD_PRODUCT_B650:
 398                 env_set("confidx", "2");
 399                 i210_index = 1;
 400                 break;
 401         case VPD_PRODUCT_B850:
 402                 env_set("confidx", "3");
 403                 i210_index = 2;
 404                 break;
 405         }
 406
 407         if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
 408                 eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
 409 }
 410
 411 static iomux_v3_cfg_t const misc_pads[] = {
 412         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(NO_PAD_CTRL),
 413         MX6_PAD_EIM_A25__GPIO5_IO02     | MUX_PAD_CTRL(NC_PAD_CTRL),
 414         MX6_PAD_EIM_CS0__GPIO2_IO23     | MUX_PAD_CTRL(NC_PAD_CTRL),
 415         MX6_PAD_EIM_CS1__GPIO2_IO24     | MUX_PAD_CTRL(NC_PAD_CTRL),
 416         MX6_PAD_EIM_OE__GPIO2_IO25      | MUX_PAD_CTRL(NC_PAD_CTRL),
 417         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(NC_PAD_CTRL),
 418         MX6_PAD_GPIO_1__GPIO1_IO01      | MUX_PAD_CTRL(NC_PAD_CTRL),
 419         MX6_PAD_GPIO_9__WDOG1_B         | MUX_PAD_CTRL(NC_PAD_CTRL),
 420 };
 421 #define SUS_S3_OUT      IMX_GPIO_NR(4, 11)
 422 #define WIFI_EN IMX_GPIO_NR(6, 14)
 423
 424 int board_early_init_f(void)
 425 {
 426         imx_iomux_v3_setup_multiple_pads(misc_pads,
 427                                          ARRAY_SIZE(misc_pads));
 428
 429         setup_iomux_uart();
 430
 431 #if defined(CONFIG_VIDEO_IPUV3)
 432         /* Set LDB clock to Video PLL */
 433         select_ldb_di_clock_source(MXC_PLL5_CLK);
 434 #endif
 435         return 0;
 436 }
 437
 438 static void set_confidx(const struct vpd_cache* vpd)
 439 {
 440         switch (vpd->product_id) {
 441         case VPD_PRODUCT_B450:
 442                 confidx = 1;
 443                 break;
 444         case VPD_PRODUCT_B650:
 445                 confidx = 2;
 446                 break;
 447         case VPD_PRODUCT_B850:
 448                 confidx = 3;
 449                 break;
 450         }
 451 }
 452
 453 int board_init(void)
 454 {
 455         if (!read_vpd(&vpd, vpd_callback)) {
 456                 int ret, rescan;
 457
 458                 vpd.is_read = true;
 459                 set_confidx(&vpd);
 460
 461                 ret = fdtdec_resetup(&rescan);
 462                 if (!ret && rescan) {
 463                         dm_uninit();
 464                         dm_init_and_scan(false);
 465                 }
 466         }
 467
 468         gpio_request(SUS_S3_OUT, "sus_s3_out");
 469         gpio_direction_output(SUS_S3_OUT, 1);
 470
 471         gpio_request(WIFI_EN, "wifi_en");
 472         gpio_direction_output(WIFI_EN, 1);
 473
 474 #if defined(CONFIG_VIDEO_IPUV3)
 475         if (is_b850v3())
 476                 setup_display_b850v3();
 477         else
 478                 setup_display_bx50v3();
 479
 480         gpio_request(LVDS_BACKLIGHT_GP, "lvds_backlight");
 481         gpio_direction_input(LVDS_BACKLIGHT_GP);
 482 #endif
 483
 484         /* address of boot parameters */
 485         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 486
 487         return 0;
 488 }
 489
 490 #ifdef CONFIG_CMD_BMODE
 491 static const struct boot_mode board_boot_modes[] = {
 492         /* 4 bit bus width */
 493         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 494         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 495         {NULL,   0},
 496 };
 497 #endif
 498
 499 void pmic_init(void)
 500 {
 501         struct udevice *reg;
 502         int ret, i;
 503         static const char * const bucks[] = {
 504                 "bcore1",
 505                 "bcore2",
 506                 "bpro",
 507                 "bmem",
 508                 "bio",
 509                 "bperi",
 510         };
 511
 512         for (i = 0; i < ARRAY_SIZE(bucks); i++) {
 513                 ret = regulator_get_by_devname(bucks[i], &reg);
 514                 if (reg < 0) {
 515                         printf("%s(): Unable to get regulator %s: %d\n",
 516                                __func__, bucks[i], ret);
 517                         continue;
 518                 }
 519                 regulator_set_mode(reg, DA9063_BUCKMODE_SYNC);
 520         }
 521 }
 522
 523 int board_late_init(void)
 524 {
 525         process_vpd(&vpd);
 526
 527 #ifdef CONFIG_CMD_BMODE
 528         add_board_boot_modes(board_boot_modes);
 529 #endif
 530
 531         if (is_b850v3())
 532                 env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
 533         else
 534                 env_set("videoargs", "video=LVDS-1:1024x768@65");
 535
 536         /* board specific pmic init */
 537         pmic_init();
 538
 539         check_time();
 540
 541         pci_init();
 542
 543         return 0;
 544 }
 545
 546 /*
 547  * Removes the 'eth[0-9]*addr' environment variable with the given index
 548  *
 549  * @param index [in] the index of the eth_device whose variable is to be removed
 550  */
 551 static void remove_ethaddr_env_var(int index)
 552 {
 553         char env_var_name[9];
 554
 555         sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
 556         env_set(env_var_name, NULL);
 557 }
 558
 559 int last_stage_init(void)
 560 {
 561         int i;
 562
 563         /*
 564          * Remove first three ethaddr which may have been created by
 565          * function process_vpd().
 566          */
 567         for (i = 0; i < 3; ++i)
 568                 remove_ethaddr_env_var(i);
 569
 570         return 0;
 571 }
 572
 573 int checkboard(void)
 574 {
 575         printf("BOARD: %s\n", CONFIG_BOARD_NAME);
 576         return 0;
 577 }
 578
 579 #ifdef CONFIG_OF_BOARD_SETUP
 580 int ft_board_setup(void *blob, bd_t *bd)
 581 {
 582         char *rtc_status = env_get("rtc_status");
 583
 584         fdt_setprop(blob, 0, "ge,boot-ver", version_string,
 585                     strlen(version_string) + 1);
 586
 587         fdt_setprop(blob, 0, "ge,rtc-status", rtc_status,
 588                     strlen(rtc_status) + 1);
 589         return 0;
 590 }
 591 #endif
 592
 593 static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 594 {
 595 #if CONFIG_IS_ENABLED(DM_VIDEO)
 596         int ret;
 597         struct udevice *dev;
 598
 599 #ifdef CONFIG_VIDEO_IPUV3
 600         if (!is_b850v3()) {
 601                 gpio_direction_output(LVDS_POWER_GP, 1);
 602
 603                 /* We need at least 200ms between power on and backlight on
 604                  * as per specifications from CHI MEI
 605                  */
 606                 mdelay(250);
 607
 608                 /* enable backlight PWM 1 */
 609                 pwm_init(0, 0, 0);
 610
 611                 /* duty cycle 5000000ns, period: 5000000ns */
 612                 pwm_config(0, 5000000, 5000000);
 613
 614                 /* Backlight Power */
 615                 gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 616
 617                 pwm_enable(0);
 618         }
 619 #endif
 620
 621         /* Probe, to find a video device to be used to show a message on
 622          * the vidconsole.
 623          */
 624         ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
 625         if (ret)
 626                 return ret;
 627 #endif
 628
 629         return 0;
 630 }
 631
 632 U_BOOT_CMD(
 633        bx50_backlight_enable, 1,      1,      do_backlight_enable,
 634        "enable Bx50 backlight",
 635        ""
 636 );
 637
 638 int board_fit_config_name_match(const char *name)
 639 {
 640         if (!vpd.is_read)
 641                 return strcmp(name, "imx6q-bx50v3");
 642
 643         switch (vpd.product_id) {
 644         case VPD_PRODUCT_B450:
 645                 return strcmp(name, "imx6q-b450v3");
 646         case VPD_PRODUCT_B650:
 647                 return strcmp(name, "imx6q-b650v3");
 648         case VPD_PRODUCT_B850:
 649                 return strcmp(name, "imx6q-b850v3");
 650         default:
 651                 return -1;
 652         }
 653 }
 654
 655 int embedded_dtb_select(void)
 656 {
 657         vpd.is_read = false;
 658         return fdtdec_setup();
 659 }