3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/processor.h>
12 #include <asm/global_data.h>
15 #include <gdsys_fpga.h>
17 #define REFLECTION_TESTPATTERN 0xdede
18 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
20 #ifdef CONFIG_SYS_FPGA_NO_RFL_HI
21 #define REFLECTION_TESTREG reflection_low
23 #define REFLECTION_TESTREG reflection_high
26 DECLARE_GLOBAL_DATA_PTR;
28 int get_fpga_state(unsigned dev)
30 return gd->arch.fpga_state[dev];
33 int board_early_init_f(void)
37 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
38 gd->arch.fpga_state[k] = 0;
43 int board_early_init_r(void)
48 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
49 gd->arch.fpga_state[k] = 0;
56 mpc8308_set_fpga_reset(1);
60 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
62 while (!mpc8308_get_fpga_done(k)) {
65 gd->arch.fpga_state[k] |=
66 FPGA_STATE_DONE_FAILED;
74 mpc8308_set_fpga_reset(0);
76 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
78 * wait for fpga out of reset
84 FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
86 FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
87 if (val == REFLECTION_TESTPATTERN_INV)
92 gd->arch.fpga_state[k] |=
93 FPGA_STATE_REFLECTION_FAILED;