board/gdsys/mpc8308/mpc8308.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014
   4  * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <asm/processor.h>
  10 #include <asm/io.h>
  11 #include <asm/global_data.h>
  12
  13 #include "mpc8308.h"
  14 #include <gdsys_fpga.h>
  15
  16 #define REFLECTION_TESTPATTERN 0xdede
  17 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
  18
  19 #ifdef CONFIG_SYS_FPGA_NO_RFL_HI
  20 #define REFLECTION_TESTREG reflection_low
  21 #else
  22 #define REFLECTION_TESTREG reflection_high
  23 #endif
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 int get_fpga_state(unsigned dev)
  28 {
  29         return gd->arch.fpga_state[dev];
  30 }
  31
  32 int board_early_init_f(void)
  33 {
  34         unsigned k;
  35
  36         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
  37                 gd->arch.fpga_state[k] = 0;
  38
  39         return 0;
  40 }
  41
  42 int board_early_init_r(void)
  43 {
  44         unsigned k;
  45         unsigned ctr;
  46
  47         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
  48                 gd->arch.fpga_state[k] = 0;
  49
  50         /*
  51          * reset FPGA
  52          */
  53         mpc8308_init();
  54
  55         mpc8308_set_fpga_reset(1);
  56
  57         mpc8308_setup_hw();
  58
  59         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
  60                 ctr = 0;
  61                 while (!mpc8308_get_fpga_done(k)) {
  62                         udelay(100000);
  63                         if (ctr++ > 5) {
  64                                 gd->arch.fpga_state[k] |=
  65                                         FPGA_STATE_DONE_FAILED;
  66                                 break;
  67                         }
  68                 }
  69         }
  70
  71         udelay(10);
  72
  73         mpc8308_set_fpga_reset(0);
  74
  75         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
  76                 /*
  77                  * wait for fpga out of reset
  78                  */
  79                 ctr = 0;
  80                 while (1) {
  81                         u16 val;
  82
  83                         FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
  84
  85                         FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
  86                         if (val == REFLECTION_TESTPATTERN_INV)
  87                                 break;
  88
  89                         udelay(100000);
  90                         if (ctr++ > 5) {
  91                                 gd->arch.fpga_state[k] |=
  92                                         FPGA_STATE_REFLECTION_FAILED;
  93                                 break;
  94                         }
  95                 }
  96         }
  97
  98         return 0;
  99 }