3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <fdt_support.h>
16 #include <fsl_esdhc.h>
18 #include <asm/fsl_serdes.h>
19 #include <asm/fsl_mpc83xx_serdes.h>
23 #include <gdsys_fpga.h>
25 #include "../common/ioep-fpga.h"
26 #include "../common/osd.h"
27 #include "../common/mclink.h"
28 #include "../common/phy.h"
29 #include "../common/fanctrl.h"
36 DECLARE_GLOBAL_DATA_PTR;
38 #define MAX_MUX_CHANNELS 2
42 MCFPGA_INIT_N = 1 << 1,
43 MCFPGA_PROGRAM_N = 1 << 2,
44 MCFPGA_UPDATE_ENABLE_N = 1 << 3,
45 MCFPGA_RESET_N = 1 << 4,
53 unsigned int mclink_fpgacount;
54 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
59 } hrcon_fans[] = CONFIG_HRCON_FANS;
61 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
70 res = mclink_send(fpga - 1, regoff, data);
72 printf("mclink_send reg %02lx data %04x returned %d\n",
82 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
91 if (fpga > mclink_fpgacount)
93 res = mclink_receive(fpga - 1, regoff, data);
95 printf("mclink_receive reg %02lx returned %d\n",
106 char *s = getenv("serial#");
107 bool hw_type_cat = pca9698_get_value(0x20, 20);
111 printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber");
123 int last_stage_init(void)
128 unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
130 bool hw_type_cat = pca9698_get_value(0x20, 20);
131 bool ch0_rgmii2_present = false;
133 FPGA_GET_REG(0, fpga_features, &fpga_features);
135 /* Turn on Parade DP501 */
136 pca9698_direction_output(0x20, 10, 1);
137 pca9698_direction_output(0x20, 11, 1);
139 ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
141 /* wait for FPGA done, then reset FPGA */
142 for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
143 unsigned int ctr = 0;
145 if (i2c_probe(mclink_controllers[k]))
148 while (!(pca953x_get_val(mclink_controllers[k])
152 printf("no done for mclink_controller %d\n", k);
157 pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
158 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
160 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
165 miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
167 for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
168 if ((mux_ch == 1) && !ch0_rgmii2_present)
171 setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
175 /* give slave-PLLs and Parade DP501 some time to be up and running */
178 mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
179 slaves = mclink_probe();
180 mclink_fpgacount = 0;
182 ioep_fpga_print_info(0);
184 #ifdef CONFIG_SYS_OSD_DH
191 mclink_fpgacount = slaves;
193 for (k = 1; k <= slaves; ++k) {
194 FPGA_GET_REG(k, fpga_features, &fpga_features);
196 ioep_fpga_print_info(k);
198 #ifdef CONFIG_SYS_OSD_DH
202 miiphy_register(bb_miiphy_buses[k].name,
203 bb_miiphy_read, bb_miiphy_write);
204 setup_88e1514(bb_miiphy_buses[k].name, 0);
208 for (k = 0; k < ARRAY_SIZE(hrcon_fans); ++k) {
209 i2c_set_bus_num(hrcon_fans[k].bus);
210 init_fan_controller(hrcon_fans[k].addr);
217 * provide access to fpga gpios and controls (for I2C bitbang)
218 * (these may look all too simple but make iocon.h much more readable)
220 void fpga_gpio_set(unsigned int bus, int pin)
222 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin);
225 void fpga_gpio_clear(unsigned int bus, int pin)
227 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin);
230 int fpga_gpio_get(unsigned int bus, int pin)
234 FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, gpio.read, &val);
239 void fpga_control_set(unsigned int bus, int pin)
243 FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val);
244 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin);
247 void fpga_control_clear(unsigned int bus, int pin)
251 FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val);
252 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val & ~pin);
255 void mpc8308_init(void)
257 pca9698_direction_output(0x20, 4, 1);
260 void mpc8308_set_fpga_reset(unsigned state)
262 pca9698_set_value(0x20, 4, state ? 0 : 1);
265 void mpc8308_setup_hw(void)
267 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
270 * set "startup-finished"-gpios
272 setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
273 setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
276 int mpc8308_get_fpga_done(unsigned fpga)
278 return pca9698_get_value(0x20, 19);
281 #ifdef CONFIG_FSL_ESDHC
282 int board_mmc_init(bd_t *bd)
284 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
285 sysconf83xx_t *sysconf = &immr->sysconf;
287 /* Enable cache snooping in eSDHC system configuration register */
288 out_be32(&sysconf->sdhccr, 0x02000000);
290 return fsl_esdhc_mmc_init(bd);
294 static struct pci_region pcie_regions_0[] = {
296 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
297 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
298 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
299 .flags = PCI_REGION_MEM,
302 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
303 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
304 .size = CONFIG_SYS_PCIE1_IO_SIZE,
305 .flags = PCI_REGION_IO,
309 void pci_init_board(void)
311 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
312 sysconf83xx_t *sysconf = &immr->sysconf;
313 law83xx_t *pcie_law = sysconf->pcielaw;
314 struct pci_region *pcie_reg[] = { pcie_regions_0 };
316 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
317 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
319 /* Deassert the resets in the control register */
320 out_be32(&sysconf->pecr1, 0xE0008000);
323 /* Configure PCI Express Local Access Windows */
324 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
325 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
327 mpc83xx_pcie_init(1, pcie_reg);
330 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
332 info->portwidth = FLASH_CFI_16BIT;
333 info->chipwidth = FLASH_CFI_BY16;
334 info->interface = FLASH_CFI_X16;
338 #if defined(CONFIG_OF_BOARD_SETUP)
339 int ft_board_setup(void *blob, bd_t *bd)
341 ft_cpu_setup(blob, bd);
342 fdt_fixup_dr_usb(blob, bd);
343 fdt_fixup_esdhc(blob, bd);
350 * FPGA MII bitbang implementation
363 static int mii_dummy_init(struct bb_miiphy_bus *bus)
368 static int mii_mdio_active(struct bb_miiphy_bus *bus)
370 struct fpga_mii *fpga_mii = bus->priv;
373 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
375 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
380 static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
382 struct fpga_mii *fpga_mii = bus->priv;
384 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
389 static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
391 struct fpga_mii *fpga_mii = bus->priv;
394 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
396 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
403 static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
406 struct fpga_mii *fpga_mii = bus->priv;
408 FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
410 *v = ((gpio & GPIO_MDIO) != 0);
415 static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
417 struct fpga_mii *fpga_mii = bus->priv;
420 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
422 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
427 static int mii_delay(struct bb_miiphy_bus *bus)
434 struct bb_miiphy_bus bb_miiphy_buses[] = {
437 .init = mii_dummy_init,
438 .mdio_active = mii_mdio_active,
439 .mdio_tristate = mii_mdio_tristate,
440 .set_mdio = mii_set_mdio,
441 .get_mdio = mii_get_mdio,
442 .set_mdc = mii_set_mdc,
444 .priv = &fpga_mii[0],
448 .init = mii_dummy_init,
449 .mdio_active = mii_mdio_active,
450 .mdio_tristate = mii_mdio_tristate,
451 .set_mdio = mii_set_mdio,
452 .get_mdio = mii_get_mdio,
453 .set_mdc = mii_set_mdc,
455 .priv = &fpga_mii[1],
459 .init = mii_dummy_init,
460 .mdio_active = mii_mdio_active,
461 .mdio_tristate = mii_mdio_tristate,
462 .set_mdio = mii_set_mdio,
463 .get_mdio = mii_get_mdio,
464 .set_mdc = mii_set_mdc,
466 .priv = &fpga_mii[2],
470 .init = mii_dummy_init,
471 .mdio_active = mii_mdio_active,
472 .mdio_tristate = mii_mdio_tristate,
473 .set_mdio = mii_set_mdio,
474 .get_mdio = mii_get_mdio,
475 .set_mdc = mii_set_mdc,
477 .priv = &fpga_mii[3],
481 int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
482 sizeof(bb_miiphy_buses[0]);