3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * Based on board/amcc/canyonlands/init.S
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm-offsets.h>
13 #include <ppc_asm.tmpl>
17 /**************************************************************************
20 * This table is used by the cpu boot code to setup the initial tlb
21 * entries. Rather than make broad assumptions in the cpu source tree,
22 * this table lets each board set things up however they like.
24 * Pointer to the table is returned in r1
26 *************************************************************************/
34 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
35 * use the speed up boot process. It is patched after relocation to
38 tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
39 4, AC_RWX | SA_G) /* TLB 0 */
42 * TLB entries for SDRAM are not needed on this platform.
43 * They are dynamically generated in the SPD DDR(2) detection
47 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
48 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
49 tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR,
53 tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC,
55 tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC,
58 /* TLB-entry for NVRAM */
59 tlbentry(CONFIG_SYS_NVRAM_BASE, SZ_1M, CONFIG_SYS_NVRAM_BASE, 4,
62 /* TLB-entry for UART */
63 tlbentry(CONFIG_SYS_UART_BASE, SZ_16K, CONFIG_SYS_UART_BASE, 4,
66 /* TLB-entry for IO */
67 tlbentry(CONFIG_SYS_IO_BASE, SZ_16K, CONFIG_SYS_IO_BASE, 4,
70 /* TLB-entry for OCM */
71 tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4,
74 /* TLB-entry for Local Configuration registers => peripherals */
75 tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS,
78 /* AHB: Internal USB Peripherals (USB, SATA) */
79 tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4,