3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <gdsys_fpga.h>
14 #define CH7301_I2C_ADDR 0x75
16 #define ICS8N3QV01_I2C_ADDR 0x6E
17 #define ICS8N3QV01_FREF 114285000
18 #define ICS8N3QV01_FREF_LL 114285000LL
19 #define ICS8N3QV01_F_DEFAULT_0 156250000LL
20 #define ICS8N3QV01_F_DEFAULT_1 125000000LL
21 #define ICS8N3QV01_F_DEFAULT_2 100000000LL
22 #define ICS8N3QV01_F_DEFAULT_3 25175000LL
24 #define SIL1178_MASTER_I2C_ADDRESS 0x38
25 #define SIL1178_SLAVE_I2C_ADDRESS 0x39
27 #define PIXCLK_640_480_60 25180000
30 #define BASE_HEIGHT 16
31 #define BUFSIZE (BASE_WIDTH * BASE_HEIGHT)
34 CH7301_CM = 0x1c, /* Clock Mode Register */
35 CH7301_IC = 0x1d, /* Input Clock Register */
36 CH7301_GPIO = 0x1e, /* GPIO Control Register */
37 CH7301_IDF = 0x1f, /* Input Data Format Register */
38 CH7301_CD = 0x20, /* Connection Detect Register */
39 CH7301_DC = 0x21, /* DAC Control Register */
40 CH7301_HPD = 0x23, /* Hot Plug Detection Register */
41 CH7301_TCTL = 0x31, /* DVI Control Input Register */
42 CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */
43 CH7301_TPD = 0x34, /* DVI PLL Divide Register */
44 CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */
45 CH7301_TPF = 0x36, /* DVI PLL Filter Register */
46 CH7301_TCT = 0x37, /* DVI Clock Test Register */
47 CH7301_TSTP = 0x48, /* Test Pattern Register */
48 CH7301_PM = 0x49, /* Power Management register */
49 CH7301_VID = 0x4a, /* Version ID Register */
50 CH7301_DID = 0x4b, /* Device ID Register */
51 CH7301_DSP = 0x56, /* DVI Sync polarity Register */
54 #if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178)
55 static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
60 FPGA_GET_REG(screen, extended_interrupt, &val);
61 } while (val & (1 << 12));
63 FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg | (data << 8));
64 FPGA_SET_REG(screen, i2c.write_mailbox, 0xc400 | (slave << 1));
67 static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg)
73 FPGA_GET_REG(screen, extended_interrupt, &val);
74 } while (val & (1 << 12));
76 FPGA_SET_REG(screen, extended_interrupt, 1 << 14);
77 FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg);
78 FPGA_SET_REG(screen, i2c.write_mailbox, 0xc000 | (slave << 1));
80 FPGA_GET_REG(screen, extended_interrupt, &val);
81 while (!(val & (1 << 14))) {
84 printf("iic receive timeout\n");
87 FPGA_GET_REG(screen, extended_interrupt, &val);
90 FPGA_GET_REG(screen, i2c.read_mailbox_ext, &val);
95 #ifdef CONFIG_SYS_MPC92469AC
96 static void mpc92469ac_calc_parameters(unsigned int fout,
97 unsigned int *post_div, unsigned int *feedback_div)
99 unsigned int n = *post_div;
100 unsigned int m = *feedback_div;
102 unsigned int b = 14745600 / 16;
106 else if (fout < 100339199)
108 else if (fout < 200678399)
113 a = fout * n + (b / 2); /* add b/2 for proper rounding */
121 static void mpc92469ac_set(unsigned screen, unsigned int fout)
125 unsigned int bitval = 0;
126 mpc92469ac_calc_parameters(fout, &n, &m);
143 FPGA_SET_REG(screen, mpc3w_control, (bitval << 9) | m);
147 #ifdef CONFIG_SYS_ICS8N3QV01
149 static unsigned int ics8n3qv01_get_fout_calc(unsigned screen, unsigned index)
151 unsigned long long n;
152 unsigned long long mint;
153 unsigned long long mfrac;
154 u8 reg_a, reg_b, reg_c, reg_d, reg_f;
155 unsigned long long fout_calc;
160 reg_a = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0 + index);
161 reg_b = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 4 + index);
162 reg_c = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 8 + index);
163 reg_d = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 12 + index);
164 reg_f = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20 + index);
166 mint = ((reg_a >> 1) & 0x1f) | (reg_f & 0x20);
167 mfrac = ((reg_a & 0x01) << 17) | (reg_b << 9) | (reg_c << 1)
171 fout_calc = (mint * ICS8N3QV01_FREF_LL
172 + mfrac * ICS8N3QV01_FREF_LL / 262144LL
173 + ICS8N3QV01_FREF_LL / 524288LL
183 static void ics8n3qv01_calc_parameters(unsigned int fout,
184 unsigned int *_mint, unsigned int *_mfrac,
188 unsigned int foutiic;
189 unsigned int fvcoiic;
191 unsigned long long mfrac;
193 n = (2215000000U + fout / 2) / fout;
194 if ((n & 1) && (n > 5))
197 foutiic = fout - (fout / 10000);
198 fvcoiic = foutiic * n;
200 mint = fvcoiic / 114285000;
201 if ((mint < 17) || (mint > 63))
202 printf("ics8n3qv01_calc_parameters: cannot determine mint\n");
204 mfrac = ((unsigned long long)fvcoiic % 114285000LL) * 262144LL
212 static void ics8n3qv01_set(unsigned screen, unsigned int fout)
217 unsigned int fout_calc;
218 unsigned long long fout_prog;
220 u8 reg0, reg4, reg8, reg12, reg18, reg20;
222 fout_calc = ics8n3qv01_get_fout_calc(screen, 1);
223 off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000
224 / ICS8N3QV01_F_DEFAULT_1;
225 printf(" PLL is off by %lld ppm\n", off_ppm);
226 fout_prog = (unsigned long long)fout * (unsigned long long)fout_calc
227 / ICS8N3QV01_F_DEFAULT_1;
228 ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n);
230 reg0 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
231 reg0 |= (mint & 0x1f) << 1;
232 reg0 |= (mfrac >> 17) & 0x01;
233 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 0, reg0);
236 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 4, reg4);
239 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 8, reg8);
243 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 12, reg12);
245 reg18 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 18) & 0x03;
247 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 18, reg18);
249 reg20 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
250 reg20 |= mint & (1 << 5);
251 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 20, reg20);
255 static int osd_write_videomem(unsigned screen, unsigned offset,
256 u16 *data, size_t charcount)
260 for (k = 0; k < charcount; ++k) {
261 if (offset + k >= BUFSIZE)
263 FPGA_SET_REG(screen, videomem[offset + k], data[k]);
269 static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
273 for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) {
289 x = simple_strtoul(argv[1], NULL, 16);
290 y = simple_strtoul(argv[2], NULL, 16);
291 color = simple_strtoul(argv[3], NULL, 16);
293 charcount = strlen(text);
294 len = (charcount > BUFSIZE) ? BUFSIZE : charcount;
296 for (k = 0; k < len; ++k)
297 buf[k] = (text[k] << 8) | color;
299 res = osd_write_videomem(screen, y * BASE_WIDTH + x, buf, len);
307 int osd_probe(unsigned screen)
315 FPGA_GET_REG(0, osd.version, &version);
316 FPGA_GET_REG(0, osd.features, &features);
318 width = ((features & 0x3f00) >> 8) + 1;
319 height = (features & 0x001f) + 1;
321 printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
322 screen, version/100, version%100, width, height);
324 #ifdef CONFIG_SYS_CH7301
325 value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
327 printf(" Probing CH7301 failed, DID %02x\n", value);
330 i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
331 i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
332 i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
333 i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
334 i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
337 #ifdef CONFIG_SYS_MPC92469AC
338 mpc92469ac_set(screen, PIXCLK_640_480_60);
341 #ifdef CONFIG_SYS_ICS8N3QV01
342 ics8n3qv01_set(screen, PIXCLK_640_480_60);
345 #ifdef CONFIG_SYS_SIL1178
346 value = fpga_iic_read(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x02);
348 printf(" Probing CH7301 SIL1178, DEV_IDL %02x\n", value);
351 /* magic initialization sequence adapted from datasheet */
352 fpga_iic_write(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
353 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
354 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
355 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
356 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
357 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
358 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
359 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
360 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
361 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
364 FPGA_SET_REG(screen, videocontrol, 0x0002);
365 FPGA_SET_REG(screen, osd.control, 0x0049);
367 FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) | (16 - 1));
368 FPGA_SET_REG(screen, osd.x_pos, 0x007f);
369 FPGA_SET_REG(screen, osd.y_pos, 0x005f);
375 int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
379 for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) {
383 u16 buffer[BASE_WIDTH];
386 unsigned count = (argc > 4) ?
387 simple_strtoul(argv[4], NULL, 16) : 1;
389 if ((argc < 4) || (strlen(argv[3]) % 4)) {
394 x = simple_strtoul(argv[1], NULL, 16);
395 y = simple_strtoul(argv[2], NULL, 16);
402 memcpy(substr, rp, 4);
404 *wp = simple_strtoul(substr, NULL, 16);
408 if (wp - buffer > BASE_WIDTH)
412 for (k = 0; k < count; ++k) {
414 y * BASE_WIDTH + x + k * (wp - buffer);
415 osd_write_videomem(screen, offset, buffer,
424 osdw, 5, 0, osd_write,
425 "write 16-bit hex encoded buffer to osd memory",
426 "pos_x pos_y buffer count\n"
430 osdp, 5, 0, osd_print,
431 "write ASCII buffer to osd memory",
432 "pos_x pos_y color text\n"