board/gdsys/common/ioep-fpga.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014
   4  * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   5  */
   6
   7 #ifdef CONFIG_GDSYS_LEGACY_DRIVERS
   8
   9 #include <common.h>
  10
  11 #include <gdsys_fpga.h>
  12
  13 enum pcb_video_type {
  14         PCB_DVI_SL,
  15         PCB_DP_165MPIX,
  16         PCB_DP_300MPIX,
  17         PCB_HDMI,
  18         PCB_DP_1_2,
  19         PCB_HDMI_2_0,
  20 };
  21
  22 enum pcb_transmission_type {
  23         PCB_CAT_1G,
  24         PCB_FIBER_3G,
  25         PCB_CAT_10G,
  26         PCB_FIBER_10G,
  27 };
  28
  29 enum carrier_speed {
  30         CARRIER_SPEED_1G,
  31         CARRIER_SPEED_3G,
  32         CARRIER_SPEED_2_5G = CARRIER_SPEED_3G,
  33         CARRIER_SPEED_10G,
  34 };
  35
  36 enum ram_config {
  37         RAM_DDR2_32BIT_295MBPS,
  38         RAM_DDR3_32BIT_590MBPS,
  39         RAM_DDR3_48BIT_590MBPS,
  40         RAM_DDR3_64BIT_1800MBPS,
  41         RAM_DDR3_48BIT_1800MBPS,
  42 };
  43
  44 enum sysclock {
  45         SYSCLK_147456,
  46 };
  47
  48 struct fpga_versions {
  49         bool video_channel;
  50         bool con_side;
  51         enum pcb_video_type pcb_video_type;
  52         enum pcb_transmission_type pcb_transmission_type;
  53         unsigned int hw_version;
  54 };
  55
  56 struct fpga_features {
  57         u8 video_channels;
  58         u8 carriers;
  59         enum carrier_speed carrier_speed;
  60         enum ram_config ram_config;
  61         enum sysclock sysclock;
  62
  63         bool pcm_tx;
  64         bool pcm_rx;
  65         bool spdif_tx;
  66         bool spdif_rx;
  67         bool usb2;
  68         bool rs232;
  69         bool compression_type1;
  70         bool compression_type2;
  71         bool compression_type3;
  72         bool interlace;
  73         bool osd;
  74         bool compression_pipes;
  75 };
  76
  77 #ifdef CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM
  78
  79 static int get_versions(unsigned int fpga, struct fpga_versions *versions)
  80 {
  81         enum {
  82                 VERSIONS_FPGA_VIDEO_CHANNEL = BIT(12),
  83                 VERSIONS_FPGA_CON_SIDE = BIT(13),
  84                 VERSIONS_FPGA_SC = BIT(14),
  85                 VERSIONS_PCB_CON = BIT(9),
  86                 VERSIONS_PCB_SC = BIT(8),
  87                 VERSIONS_PCB_VIDEO_MASK = 0x3 << 6,
  88                 VERSIONS_PCB_VIDEO_DP_1_2 = 0x0 << 6,
  89                 VERSIONS_PCB_VIDEO_HDMI_2_0 = 0x1 << 6,
  90                 VERSIONS_PCB_TRANSMISSION_MASK = 0x3 << 4,
  91                 VERSIONS_PCB_TRANSMISSION_FIBER_10G = 0x0 << 4,
  92                 VERSIONS_PCB_TRANSMISSION_CAT_10G = 0x1 << 4,
  93                 VERSIONS_PCB_TRANSMISSION_FIBER_3G = 0x2 << 4,
  94                 VERSIONS_PCB_TRANSMISSION_CAT_1G = 0x3 << 4,
  95                 VERSIONS_HW_VER_MASK = 0xf << 0,
  96         };
  97         u16 raw_versions;
  98
  99         memset(versions, 0, sizeof(struct fpga_versions));
 100
 101         FPGA_GET_REG(fpga, versions, &raw_versions);
 102
 103         versions->video_channel = raw_versions & VERSIONS_FPGA_VIDEO_CHANNEL;
 104         versions->con_side = raw_versions & VERSIONS_FPGA_CON_SIDE;
 105
 106         switch (raw_versions & VERSIONS_PCB_VIDEO_MASK) {
 107         case VERSIONS_PCB_VIDEO_DP_1_2:
 108                 versions->pcb_video_type = PCB_DP_1_2;
 109                 break;
 110
 111         case VERSIONS_PCB_VIDEO_HDMI_2_0:
 112                 versions->pcb_video_type = PCB_HDMI_2_0;
 113                 break;
 114         }
 115
 116         switch (raw_versions & VERSIONS_PCB_TRANSMISSION_MASK) {
 117         case VERSIONS_PCB_TRANSMISSION_FIBER_10G:
 118                 versions->pcb_transmission_type = PCB_FIBER_10G;
 119                 break;
 120
 121         case VERSIONS_PCB_TRANSMISSION_CAT_10G:
 122                 versions->pcb_transmission_type = PCB_CAT_10G;
 123                 break;
 124
 125         case VERSIONS_PCB_TRANSMISSION_FIBER_3G:
 126                 versions->pcb_transmission_type = PCB_FIBER_3G;
 127                 break;
 128
 129         case VERSIONS_PCB_TRANSMISSION_CAT_1G:
 130                 versions->pcb_transmission_type = PCB_CAT_1G;
 131                 break;
 132
 133         }
 134
 135         versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
 136
 137         return 0;
 138 }
 139
 140 static int get_features(unsigned int fpga, struct fpga_features *features)
 141 {
 142         enum {
 143                 FEATURE_SPDIF_RX = BIT(15),
 144                 FEATURE_SPDIF_TX = BIT(14),
 145                 FEATURE_PCM_RX = BIT(13),
 146                 FEATURE_PCM_TX = BIT(12),
 147                 FEATURE_RAM_MASK = GENMASK(11, 8),
 148                 FEATURE_RAM_DDR2_32BIT_295MBPS = 0x0 << 8,
 149                 FEATURE_RAM_DDR3_32BIT_590MBPS = 0x1 << 8,
 150                 FEATURE_RAM_DDR3_48BIT_590MBPS = 0x2 << 8,
 151                 FEATURE_RAM_DDR3_64BIT_1800MBPS = 0x3 << 8,
 152                 FEATURE_RAM_DDR3_48BIT_1800MBPS = 0x4 << 8,
 153                 FEATURE_CARRIER_SPEED_MASK = GENMASK(7, 6),
 154                 FEATURE_CARRIER_SPEED_1G = 0x0 << 6,
 155                 FEATURE_CARRIER_SPEED_2_5G = 0x1 << 6,
 156                 FEATURE_CARRIER_SPEED_10G = 0x2 << 6,
 157                 FEATURE_CARRIERS_MASK = GENMASK(5, 4),
 158                 FEATURE_CARRIERS_0 = 0x0 << 4,
 159                 FEATURE_CARRIERS_1 = 0x1 << 4,
 160                 FEATURE_CARRIERS_2 = 0x2 << 4,
 161                 FEATURE_CARRIERS_4 = 0x3 << 4,
 162                 FEATURE_USB2 = BIT(3),
 163                 FEATURE_VIDEOCHANNELS_MASK = GENMASK(2, 0),
 164                 FEATURE_VIDEOCHANNELS_0 = 0x0 << 0,
 165                 FEATURE_VIDEOCHANNELS_1 = 0x1 << 0,
 166                 FEATURE_VIDEOCHANNELS_1_1 = 0x2 << 0,
 167                 FEATURE_VIDEOCHANNELS_2 = 0x3 << 0,
 168         };
 169
 170         enum {
 171                 EXT_FEATURE_OSD = BIT(15),
 172                 EXT_FEATURE_ETHERNET = BIT(9),
 173                 EXT_FEATURE_INTERLACE = BIT(8),
 174                 EXT_FEATURE_RS232 = BIT(7),
 175                 EXT_FEATURE_COMPRESSION_PERF_MASK = GENMASK(6, 4),
 176                 EXT_FEATURE_COMPRESSION_PERF_1X = 0x0 << 4,
 177                 EXT_FEATURE_COMPRESSION_PERF_2X = 0x1 << 4,
 178                 EXT_FEATURE_COMPRESSION_PERF_4X = 0x2 << 4,
 179                 EXT_FEATURE_COMPRESSION_TYPE1 = BIT(0),
 180                 EXT_FEATURE_COMPRESSION_TYPE2 = BIT(1),
 181                 EXT_FEATURE_COMPRESSION_TYPE3 = BIT(2),
 182         };
 183
 184         u16 raw_features;
 185         u16 raw_extended_features;
 186
 187         memset(features, 0, sizeof(struct fpga_features));
 188
 189         FPGA_GET_REG(fpga, fpga_features, &raw_features);
 190         FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features);
 191
 192         switch (raw_features & FEATURE_VIDEOCHANNELS_MASK) {
 193         case FEATURE_VIDEOCHANNELS_0:
 194                 features->video_channels = 0;
 195                 break;
 196
 197         case FEATURE_VIDEOCHANNELS_1:
 198                 features->video_channels = 1;
 199                 break;
 200
 201         case FEATURE_VIDEOCHANNELS_1_1:
 202         case FEATURE_VIDEOCHANNELS_2:
 203                 features->video_channels = 2;
 204                 break;
 205         };
 206
 207         switch (raw_features & FEATURE_CARRIERS_MASK) {
 208         case FEATURE_CARRIERS_0:
 209                 features->carriers = 0;
 210                 break;
 211
 212         case FEATURE_CARRIERS_1:
 213                 features->carriers = 1;
 214                 break;
 215
 216         case FEATURE_CARRIERS_2:
 217                 features->carriers = 2;
 218                 break;
 219
 220         case FEATURE_CARRIERS_4:
 221                 features->carriers = 4;
 222                 break;
 223         }
 224
 225         switch (raw_features & FEATURE_CARRIER_SPEED_MASK) {
 226         case FEATURE_CARRIER_SPEED_1G:
 227                 features->carrier_speed = CARRIER_SPEED_1G;
 228                 break;
 229         case FEATURE_CARRIER_SPEED_2_5G:
 230                 features->carrier_speed = CARRIER_SPEED_2_5G;
 231                 break;
 232         case FEATURE_CARRIER_SPEED_10G:
 233                 features->carrier_speed = CARRIER_SPEED_10G;
 234                 break;
 235         }
 236
 237         switch (raw_features & FEATURE_RAM_MASK) {
 238         case FEATURE_RAM_DDR2_32BIT_295MBPS:
 239                 features->ram_config = RAM_DDR2_32BIT_295MBPS;
 240                 break;
 241
 242         case FEATURE_RAM_DDR3_32BIT_590MBPS:
 243                 features->ram_config = RAM_DDR3_32BIT_590MBPS;
 244                 break;
 245
 246         case FEATURE_RAM_DDR3_48BIT_590MBPS:
 247                 features->ram_config = RAM_DDR3_48BIT_590MBPS;
 248                 break;
 249
 250         case FEATURE_RAM_DDR3_64BIT_1800MBPS:
 251                 features->ram_config = RAM_DDR3_64BIT_1800MBPS;
 252                 break;
 253
 254         case FEATURE_RAM_DDR3_48BIT_1800MBPS:
 255                 features->ram_config = RAM_DDR3_48BIT_1800MBPS;
 256                 break;
 257         }
 258
 259         features->pcm_tx = raw_features & FEATURE_PCM_TX;
 260         features->pcm_rx = raw_features & FEATURE_PCM_RX;
 261         features->spdif_tx = raw_features & FEATURE_SPDIF_TX;
 262         features->spdif_rx = raw_features & FEATURE_SPDIF_RX;
 263         features->usb2 = raw_features & FEATURE_USB2;
 264         features->rs232 = raw_extended_features & EXT_FEATURE_RS232;
 265         features->compression_type1 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE1;
 266         features->compression_type2 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE2;
 267         features->compression_type3 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE3;
 268         features->interlace = raw_extended_features & EXT_FEATURE_INTERLACE;
 269         features->osd = raw_extended_features & EXT_FEATURE_OSD;
 270         features->compression_pipes = raw_extended_features & EXT_FEATURE_COMPRESSION_PERF_MASK;
 271
 272         return 0;
 273 }
 274
 275 #else
 276
 277 static int get_versions(unsigned int fpga, struct fpga_versions *versions)
 278 {
 279         enum {
 280                 /* HW version encoding is a mess, leave it for the moment */
 281                 VERSIONS_HW_VER_MASK = 0xf << 0,
 282                 VERSIONS_PIX_CLOCK_GEN_IDT8N3QV01 = BIT(4),
 283                 VERSIONS_SFP = BIT(5),
 284                 VERSIONS_VIDEO_MASK = 0x7 << 6,
 285                 VERSIONS_VIDEO_DVI = 0x0 << 6,
 286                 VERSIONS_VIDEO_DP_165 = 0x1 << 6,
 287                 VERSIONS_VIDEO_DP_300 = 0x2 << 6,
 288                 VERSIONS_VIDEO_HDMI = 0x3 << 6,
 289                 VERSIONS_UT_MASK = 0xf << 12,
 290                 VERSIONS_UT_MAIN_SERVER = 0x0 << 12,
 291                 VERSIONS_UT_MAIN_USER = 0x1 << 12,
 292                 VERSIONS_UT_VIDEO_SERVER = 0x2 << 12,
 293                 VERSIONS_UT_VIDEO_USER = 0x3 << 12,
 294         };
 295         u16 raw_versions;
 296
 297         memset(versions, 0, sizeof(struct fpga_versions));
 298
 299         FPGA_GET_REG(fpga, versions, &raw_versions);
 300
 301         switch (raw_versions & VERSIONS_UT_MASK) {
 302         case VERSIONS_UT_MAIN_SERVER:
 303                 versions->video_channel = false;
 304                 versions->con_side = false;
 305                 break;
 306
 307         case VERSIONS_UT_MAIN_USER:
 308                 versions->video_channel = false;
 309                 versions->con_side = true;
 310                 break;
 311
 312         case VERSIONS_UT_VIDEO_SERVER:
 313                 versions->video_channel = true;
 314                 versions->con_side = false;
 315                 break;
 316
 317         case VERSIONS_UT_VIDEO_USER:
 318                 versions->video_channel = true;
 319                 versions->con_side = true;
 320                 break;
 321
 322         }
 323
 324         switch (raw_versions & VERSIONS_VIDEO_MASK) {
 325         case VERSIONS_VIDEO_DVI:
 326                 versions->pcb_video_type = PCB_DVI_SL;
 327                 break;
 328
 329         case VERSIONS_VIDEO_DP_165:
 330                 versions->pcb_video_type = PCB_DP_165MPIX;
 331                 break;
 332
 333         case VERSIONS_VIDEO_DP_300:
 334                 versions->pcb_video_type = PCB_DP_300MPIX;
 335                 break;
 336
 337         case VERSIONS_VIDEO_HDMI:
 338                 versions->pcb_video_type = PCB_HDMI;
 339                 break;
 340         }
 341
 342         versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
 343
 344         if (raw_versions & VERSIONS_SFP)
 345                 versions->pcb_transmission_type = PCB_FIBER_3G;
 346         else
 347                 versions->pcb_transmission_type = PCB_CAT_1G;
 348
 349         return 0;
 350 }
 351
 352 static int get_features(unsigned int fpga, struct fpga_features *features)
 353 {
 354         enum {
 355                 FEATURE_CARRIER_SPEED_2_5 = BIT(4),
 356                 FEATURE_RAM_MASK = 0x7 << 5,
 357                 FEATURE_RAM_DDR2_32BIT = 0x0 << 5,
 358                 FEATURE_RAM_DDR3_32BIT = 0x1 << 5,
 359                 FEATURE_RAM_DDR3_48BIT = 0x2 << 5,
 360                 FEATURE_PCM_AUDIO_TX = BIT(9),
 361                 FEATURE_PCM_AUDIO_RX = BIT(10),
 362                 FEATURE_OSD = BIT(11),
 363                 FEATURE_USB20 = BIT(12),
 364                 FEATURE_COMPRESSION_MASK = 7 << 13,
 365                 FEATURE_COMPRESSION_TYPE1 = 0x1 << 13,
 366                 FEATURE_COMPRESSION_TYPE1_TYPE2 = 0x3 << 13,
 367                 FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3 = 0x7 << 13,
 368         };
 369
 370         enum {
 371                 EXTENDED_FEATURE_SPDIF_AUDIO_TX = BIT(0),
 372                 EXTENDED_FEATURE_SPDIF_AUDIO_RX = BIT(1),
 373                 EXTENDED_FEATURE_RS232 = BIT(2),
 374                 EXTENDED_FEATURE_COMPRESSION_PIPES = BIT(3),
 375                 EXTENDED_FEATURE_INTERLACE = BIT(4),
 376         };
 377
 378         u16 raw_features;
 379 #ifdef GDSYS_LEGACY_DRIVERS
 380         u16 raw_extended_features;
 381 #endif
 382
 383         memset(features, 0, sizeof(struct fpga_features));
 384
 385         FPGA_GET_REG(fpga, fpga_features, &raw_features);
 386 #ifdef GDSYS_LEGACY_DRIVERS
 387         FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features);
 388 #endif
 389
 390         features->video_channels = raw_features & 0x3;
 391         features->carriers = (raw_features >> 2) & 0x3;
 392
 393         features->carrier_speed = (raw_features & FEATURE_CARRIER_SPEED_2_5)
 394                 ? CARRIER_SPEED_2_5G : CARRIER_SPEED_1G;
 395
 396         switch (raw_features & FEATURE_RAM_MASK) {
 397         case FEATURE_RAM_DDR2_32BIT:
 398                 features->ram_config = RAM_DDR2_32BIT_295MBPS;
 399                 break;
 400
 401         case FEATURE_RAM_DDR3_32BIT:
 402                 features->ram_config = RAM_DDR3_32BIT_590MBPS;
 403                 break;
 404
 405         case FEATURE_RAM_DDR3_48BIT:
 406                 features->ram_config = RAM_DDR3_48BIT_590MBPS;
 407                 break;
 408         }
 409
 410         features->pcm_tx = raw_features & FEATURE_PCM_AUDIO_TX;
 411         features->pcm_rx = raw_features & FEATURE_PCM_AUDIO_RX;
 412 #ifdef GDSYS_LEGACY_DRIVERS
 413         features->spdif_tx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_TX;
 414         features->spdif_rx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_RX;
 415 #endif
 416
 417         features->usb2 = raw_features & FEATURE_USB20;
 418 #ifdef GDSYS_LEGACY_DRIVERS
 419         features->rs232 = raw_extended_features & EXTENDED_FEATURE_RS232;
 420 #endif
 421
 422         features->compression_type1 = false;
 423         features->compression_type2 = false;
 424         features->compression_type3 = false;
 425         switch (raw_features & FEATURE_COMPRESSION_MASK) {
 426         case FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3:
 427                 features->compression_type3 = true;
 428         case FEATURE_COMPRESSION_TYPE1_TYPE2:
 429                 features->compression_type2 = true;
 430         case FEATURE_COMPRESSION_TYPE1:
 431                 features->compression_type1 = true;
 432                 break;
 433         }
 434
 435 #ifdef GDSYS_LEGACY_DRIVERS
 436         features->interlace = raw_extended_features & EXTENDED_FEATURE_INTERLACE;
 437 #endif
 438         features->osd = raw_features & FEATURE_OSD;
 439 #ifdef GDSYS_LEGACY_DRIVERS
 440         features->compression_pipes = raw_extended_features & EXTENDED_FEATURE_COMPRESSION_PIPES;
 441 #endif
 442
 443         return 0;
 444 }
 445
 446 #endif
 447
 448 bool ioep_fpga_has_osd(unsigned int fpga)
 449 {
 450         struct fpga_features features;
 451
 452         get_features(fpga, &features);
 453
 454         return features.osd;
 455 }
 456
 457 void ioep_fpga_print_info(unsigned int fpga)
 458 {
 459         u16 fpga_version;
 460         struct fpga_versions versions;
 461         struct fpga_features features;
 462
 463         FPGA_GET_REG(fpga, fpga_version, &fpga_version);
 464         get_versions(fpga, &versions);
 465         get_features(fpga, &features);
 466
 467         if (versions.video_channel)
 468                 printf("Videochannel");
 469         else
 470                 printf("Mainchannel");
 471
 472         if (versions.con_side)
 473                 printf(" User");
 474         else
 475                 printf(" Server");
 476
 477 // FIXME
 478 #if 0
 479                 if (versions & (1<<4))
 480                         printf(" UC");
 481 #endif
 482
 483         switch(versions.pcb_transmission_type) {
 484         case PCB_CAT_1G:
 485         case PCB_CAT_10G:
 486                 printf(" CAT");
 487                 break;
 488         case PCB_FIBER_3G:
 489         case PCB_FIBER_10G:
 490                 printf(" Fiber");
 491                 break;
 492         };
 493
 494         switch (versions.pcb_video_type) {
 495         case PCB_DVI_SL:
 496                 printf(" DVI,");
 497                 break;
 498         case PCB_DP_165MPIX:
 499                 printf(" DP 165MPix/s,");
 500                 break;
 501         case PCB_DP_300MPIX:
 502                 printf(" DP 300MPix/s,");
 503                 break;
 504         case PCB_HDMI:
 505                 printf(" HDMI,");
 506                 break;
 507         case PCB_DP_1_2:
 508                 printf(" DP 1.2,");
 509                 break;
 510         case PCB_HDMI_2_0:
 511                 printf(" HDMI 2.0,");
 512                 break;
 513         }
 514
 515         printf(" FPGA V %d.%02d\n       features: ",
 516                fpga_version / 100, fpga_version % 100);
 517
 518         if (!features.compression_type1 &&
 519             !features.compression_type2 &&
 520             !features.compression_type3)
 521                 printf("no compression, ");
 522
 523         if (features.compression_type1)
 524                 printf("type1, ");
 525
 526         if (features.compression_type2)
 527                 printf("type2, ");
 528
 529         if (features.compression_type3)
 530                 printf("type3, ");
 531
 532         printf("%sosd", features.osd ? "" : "no ");
 533
 534         if (features.pcm_rx && features.pcm_tx)
 535                 printf(", pcm rx+tx");
 536         else if(features.pcm_rx)
 537                 printf(", pcm rx");
 538         else if(features.pcm_tx)
 539                 printf(", pcm tx");
 540
 541         if (features.spdif_rx && features.spdif_tx)
 542                 printf(", spdif rx+tx");
 543         else if(features.spdif_rx)
 544                 printf(", spdif rx");
 545         else if(features.spdif_tx)
 546                 printf(", spdif tx");
 547
 548         puts(",\n       ");
 549
 550         switch (features.sysclock) {
 551         case SYSCLK_147456:
 552                 printf("clock 147.456 MHz");
 553                 break;
 554         }
 555
 556         switch (features.ram_config) {
 557         case RAM_DDR2_32BIT_295MBPS:
 558                 printf(", RAM 32 bit DDR2");
 559                 break;
 560         case RAM_DDR3_32BIT_590MBPS:
 561                 printf(", RAM 32 bit DDR3");
 562                 break;
 563         case RAM_DDR3_48BIT_590MBPS:
 564         case RAM_DDR3_48BIT_1800MBPS:
 565                 printf(", RAM 48 bit DDR3");
 566                 break;
 567         case RAM_DDR3_64BIT_1800MBPS:
 568                 printf(", RAM 64 bit DDR3");
 569                 break;
 570         }
 571
 572         printf(", %d carrier(s)", features.carriers);
 573
 574         switch(features.carrier_speed) {
 575         case CARRIER_SPEED_1G:
 576                 printf(", 1Gbit/s");
 577                 break;
 578         case CARRIER_SPEED_3G:
 579                 printf(", 3Gbit/s");
 580                 break;
 581         case CARRIER_SPEED_10G:
 582                 printf(", 10Gbit/s");
 583                 break;
 584         }
 585
 586         printf(", %d video channel(s)\n", features.video_channels);
 587 }
 588
 589 #endif /* CONFIG_GDSYS_LEGACY_DRIVERS */