3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/processor.h>
13 #include <asm/ppc4xx-gpio.h>
16 #include <gdsys_fpga.h>
18 #include "../common/osd.h"
19 #include "../common/mclink.h"
27 DECLARE_GLOBAL_DATA_PTR;
29 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
30 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
31 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
33 #define MAX_MUX_CHANNELS 2
36 UNITTYPE_MAIN_SERVER = 0,
37 UNITTYPE_MAIN_USER = 1,
38 UNITTYPE_VIDEO_SERVER = 2,
39 UNITTYPE_VIDEO_USER = 3,
60 COMPRESSION_TYPE1_DELTA = 1,
61 COMPRESSION_TYPE1_TYPE2_DELTA = 3,
82 CARRIER_SPEED_2_5G = 1,
87 MCFPGA_INIT_N = 1 << 1,
88 MCFPGA_PROGRAM_N = 1 << 2,
89 MCFPGA_UPDATE_ENABLE_N = 1 << 3,
90 MCFPGA_RESET_N = 1 << 4,
98 unsigned int mclink_fpgacount;
99 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
101 static int setup_88e1518(const char *bus, unsigned char addr);
103 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
112 res = mclink_send(fpga - 1, regoff, data);
114 printf("mclink_send reg %02lx data %04x returned %d\n",
124 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
130 *data = in_le16(reg);
133 if (fpga > mclink_fpgacount)
135 res = mclink_receive(fpga - 1, regoff, data);
137 printf("mclink_receive reg %02lx returned %d\n",
147 * Check Board Identity:
151 char *s = getenv("serial#");
167 static void print_fpga_info(unsigned int fpga, bool rgmii2_present)
173 unsigned hardware_version;
174 unsigned feature_compression;
175 unsigned feature_osd;
176 unsigned feature_audio;
177 unsigned feature_sysclock;
178 unsigned feature_ramconfig;
179 unsigned feature_carrier_speed;
180 unsigned feature_carriers;
181 unsigned feature_video_channels;
183 int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
185 FPGA_GET_REG(0, versions, &versions);
186 FPGA_GET_REG(0, fpga_version, &fpga_version);
187 FPGA_GET_REG(0, fpga_features, &fpga_features);
189 unit_type = (versions & 0xf000) >> 12;
190 feature_compression = (fpga_features & 0xe000) >> 13;
191 feature_osd = fpga_features & (1<<11);
192 feature_audio = (fpga_features & 0x0600) >> 9;
193 feature_sysclock = (fpga_features & 0x0180) >> 7;
194 feature_ramconfig = (fpga_features & 0x0060) >> 5;
195 feature_carrier_speed = fpga_features & (1<<4);
196 feature_carriers = (fpga_features & 0x000c) >> 2;
197 feature_video_channels = fpga_features & 0x0003;
203 case UNITTYPE_MAIN_USER:
204 printf("Mainchannel");
207 case UNITTYPE_VIDEO_USER:
208 printf("Videochannel");
212 printf("UnitType %d(not supported)", unit_type);
216 if (unit_type == UNITTYPE_MAIN_USER) {
219 (in_le16((void *)LATCH2_BASE)>>8) & 0x0f;
222 (!!pca9698_get_value(0x20, 24) << 0)
223 | (!!pca9698_get_value(0x20, 25) << 1)
224 | (!!pca9698_get_value(0x20, 26) << 2)
225 | (!!pca9698_get_value(0x20, 27) << 3);
226 switch (hardware_version) {
228 printf(" HW-Ver 1.00,");
232 printf(" HW-Ver 1.04,");
236 printf(" HW-Ver 1.10,");
240 printf(" HW-Ver 1.20-1.21,");
244 printf(" HW-Ver 2.00,");
248 printf(" HW-Ver 2.10,");
252 printf(" HW-Ver 2.20,");
256 printf(" HW-Ver 2.30,");
260 printf(" HW-Ver %d(not supported),",
268 if (unit_type == UNITTYPE_VIDEO_USER) {
269 hardware_version = versions & 0x000f;
270 switch (hardware_version) {
272 printf(" HW-Ver 2.00,");
276 printf(" HW-Ver 2.10,");
280 printf(" HW-Ver %d(not supported),",
286 printf(" FPGA V %d.%02d\n features:",
287 fpga_version / 100, fpga_version % 100);
290 switch (feature_compression) {
291 case COMPRESSION_NONE:
292 printf(" no compression");
295 case COMPRESSION_TYPE1_DELTA:
296 printf(" type1-deltacompression");
299 case COMPRESSION_TYPE1_TYPE2_DELTA:
300 printf(" type1-deltacompression, type2-inlinecompression");
304 printf(" compression %d(not supported)", feature_compression);
308 printf(", %sosd", feature_osd ? "" : "no ");
310 switch (feature_audio) {
312 printf(", no audio");
316 printf(", audio tx");
320 printf(", audio rx");
324 printf(", audio rx+tx");
328 printf(", audio %d(not supported)", feature_audio);
334 switch (feature_sysclock) {
336 printf("clock 147.456 MHz");
340 printf("clock %d(not supported)", feature_sysclock);
344 switch (feature_ramconfig) {
346 printf(", RAM 32 bit DDR2");
350 printf(", RAM 32 bit DDR3");
354 printf(", RAM %d(not supported)", feature_ramconfig);
358 printf(", %d carrier(s) %s", feature_carriers,
359 feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
361 printf(", %d video channel(s)\n", feature_video_channels);
364 int last_stage_init(void)
369 unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
370 int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
372 int feature_carrier_speed = fpga_features & (1<<4);
373 bool ch0_rgmii2_present = false;
375 FPGA_GET_REG(0, fpga_features, &fpga_features);
378 /* Turn on Parade DP501 */
379 pca9698_direction_output(0x20, 9, 1);
382 ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
385 print_fpga_info(0, ch0_rgmii2_present);
388 /* wait for FPGA done */
389 for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
390 unsigned int ctr = 0;
392 if (i2c_probe(mclink_controllers[k]))
395 while (!(pca953x_get_val(mclink_controllers[k])
399 printf("no done for mclink_controller %d\n", k);
405 if (!legacy && (feature_carrier_speed == CARRIER_SPEED_1G)) {
406 miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
408 for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
409 if ((mux_ch == 1) && !ch0_rgmii2_present)
412 setup_88e1518(bb_miiphy_buses[0].name, mux_ch);
416 /* wait for slave-PLLs to be up and running */
419 mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
420 slaves = mclink_probe();
421 mclink_fpgacount = 0;
426 mclink_fpgacount = slaves;
428 for (k = 1; k <= slaves; ++k) {
429 FPGA_GET_REG(k, fpga_features, &fpga_features);
430 feature_carrier_speed = fpga_features & (1<<4);
432 print_fpga_info(k, false);
434 if (feature_carrier_speed == CARRIER_SPEED_1G) {
435 miiphy_register(bb_miiphy_buses[k].name,
436 bb_miiphy_read, bb_miiphy_write);
437 setup_88e1518(bb_miiphy_buses[k].name, 0);
445 * provide access to fpga gpios (for I2C bitbang)
446 * (these may look all too simple but make iocon.h much more readable)
448 void fpga_gpio_set(unsigned int bus, int pin)
450 FPGA_SET_REG(bus, gpio.set, pin);
453 void fpga_gpio_clear(unsigned int bus, int pin)
455 FPGA_SET_REG(bus, gpio.clear, pin);
458 int fpga_gpio_get(unsigned int bus, int pin)
462 FPGA_GET_REG(bus, gpio.read, &val);
467 void gd405ep_init(void)
471 if (i2c_probe(0x20)) { /* i2c_probe returns 0 on success */
472 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
473 gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
475 pca9698_direction_output(0x20, 4, 1);
479 void gd405ep_set_fpga_reset(unsigned state)
481 int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
485 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
486 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
488 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
489 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
492 pca9698_set_value(0x20, 4, state ? 0 : 1);
496 void gd405ep_setup_hw(void)
499 * set "startup-finished"-gpios
501 gpio_write_bit(21, 0);
502 gpio_write_bit(22, 1);
505 int gd405ep_get_fpga_done(unsigned fpga)
507 int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
510 return in_le16((void *)LATCH2_BASE)
511 & CONFIG_SYS_FPGA_DONE(fpga);
513 return pca9698_get_value(0x20, 20);
517 * FPGA MII bitbang implementation
530 static int mii_dummy_init(struct bb_miiphy_bus *bus)
535 static int mii_mdio_active(struct bb_miiphy_bus *bus)
537 struct fpga_mii *fpga_mii = bus->priv;
540 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
542 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
547 static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
549 struct fpga_mii *fpga_mii = bus->priv;
551 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
556 static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
558 struct fpga_mii *fpga_mii = bus->priv;
561 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
563 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
570 static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
573 struct fpga_mii *fpga_mii = bus->priv;
575 FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
577 *v = ((gpio & GPIO_MDIO) != 0);
582 static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
584 struct fpga_mii *fpga_mii = bus->priv;
587 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
589 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
594 static int mii_delay(struct bb_miiphy_bus *bus)
601 struct bb_miiphy_bus bb_miiphy_buses[] = {
604 .init = mii_dummy_init,
605 .mdio_active = mii_mdio_active,
606 .mdio_tristate = mii_mdio_tristate,
607 .set_mdio = mii_set_mdio,
608 .get_mdio = mii_get_mdio,
609 .set_mdc = mii_set_mdc,
611 .priv = &fpga_mii[0],
615 .init = mii_dummy_init,
616 .mdio_active = mii_mdio_active,
617 .mdio_tristate = mii_mdio_tristate,
618 .set_mdio = mii_set_mdio,
619 .get_mdio = mii_get_mdio,
620 .set_mdc = mii_set_mdc,
622 .priv = &fpga_mii[1],
626 .init = mii_dummy_init,
627 .mdio_active = mii_mdio_active,
628 .mdio_tristate = mii_mdio_tristate,
629 .set_mdio = mii_set_mdio,
630 .get_mdio = mii_get_mdio,
631 .set_mdc = mii_set_mdc,
633 .priv = &fpga_mii[2],
637 .init = mii_dummy_init,
638 .mdio_active = mii_mdio_active,
639 .mdio_tristate = mii_mdio_tristate,
640 .set_mdio = mii_set_mdio,
641 .get_mdio = mii_get_mdio,
642 .set_mdc = mii_set_mdc,
644 .priv = &fpga_mii[3],
648 int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
649 sizeof(bb_miiphy_buses[0]);
655 MIICMD_WAIT_FOR_VALUE,
658 struct mii_setupcmd {
667 * verify we are talking to a 88e1518
669 struct mii_setupcmd verify_88e1518[] = {
670 { MIICMD_SET, 22, 0x0000 },
671 { MIICMD_VERIFY_VALUE, 2, 0x0141, 0xffff },
672 { MIICMD_VERIFY_VALUE, 3, 0x0dd0, 0xfff0 },
676 * workaround for erratum mentioned in 88E1518 release notes
678 struct mii_setupcmd fixup_88e1518[] = {
679 { MIICMD_SET, 22, 0x00ff },
680 { MIICMD_SET, 17, 0x214b },
681 { MIICMD_SET, 16, 0x2144 },
682 { MIICMD_SET, 17, 0x0c28 },
683 { MIICMD_SET, 16, 0x2146 },
684 { MIICMD_SET, 17, 0xb233 },
685 { MIICMD_SET, 16, 0x214d },
686 { MIICMD_SET, 17, 0xcc0c },
687 { MIICMD_SET, 16, 0x2159 },
688 { MIICMD_SET, 22, 0x00fb },
689 { MIICMD_SET, 7, 0xc00d },
690 { MIICMD_SET, 22, 0x0000 },
694 * default initialization:
695 * - set RGMII receive timing to "receive clock transition when data stable"
696 * - set RGMII transmit timing to "transmit clock internally delayed"
697 * - set RGMII output impedance target to 78,8 Ohm
698 * - run output impedance calibration
699 * - set autonegotiation advertise to 1000FD only
701 struct mii_setupcmd default_88e1518[] = {
702 { MIICMD_SET, 22, 0x0002 },
703 { MIICMD_MODIFY, 21, 0x0030, 0x0030 },
704 { MIICMD_MODIFY, 25, 0x0000, 0x0003 },
705 { MIICMD_MODIFY, 24, 0x8000, 0x8000 },
706 { MIICMD_WAIT_FOR_VALUE, 24, 0x4000, 0x4000, 2000 },
707 { MIICMD_SET, 22, 0x0000 },
708 { MIICMD_MODIFY, 4, 0x0000, 0x01e0 },
709 { MIICMD_MODIFY, 9, 0x0200, 0x0300 },
713 * turn off CLK125 for PHY daughterboard
715 struct mii_setupcmd ch1fix_88e1518[] = {
716 { MIICMD_SET, 22, 0x0002 },
717 { MIICMD_MODIFY, 16, 0x0006, 0x0006 },
718 { MIICMD_SET, 22, 0x0000 },
722 * perform copper software reset
724 struct mii_setupcmd swreset_88e1518[] = {
725 { MIICMD_SET, 22, 0x0000 },
726 { MIICMD_MODIFY, 0, 0x8000, 0x8000 },
727 { MIICMD_WAIT_FOR_VALUE, 0, 0x0000, 0x8000, 2000 },
730 static int process_setupcmd(const char *bus, unsigned char addr,
731 struct mii_setupcmd *setupcmd)
734 u8 reg = setupcmd->reg;
735 u16 data = setupcmd->data;
736 u16 mask = setupcmd->mask;
737 u32 timeout = setupcmd->timeout;
741 debug("mii %s:%u reg %2u ", bus, addr, reg);
743 switch (setupcmd->token) {
745 res = miiphy_read(bus, addr, reg, &orig_data);
748 debug("is %04x. (value %04x mask %04x) ", orig_data, data,
750 data = (orig_data & ~mask) | (data & mask);
752 debug("=> %04x\n", data);
753 res = miiphy_write(bus, addr, reg, data);
755 case MIICMD_VERIFY_VALUE:
756 res = miiphy_read(bus, addr, reg, &orig_data);
759 if ((orig_data & mask) != (data & mask))
761 debug("(value %04x mask %04x) == %04x? %s\n", data, mask,
762 orig_data, res ? "FAIL" : "PASS");
764 case MIICMD_WAIT_FOR_VALUE:
766 start = get_timer(0);
767 while ((res != 0) && (get_timer(start) < timeout)) {
768 res = miiphy_read(bus, addr, reg, &orig_data);
771 if ((orig_data & mask) != (data & mask))
774 debug("(value %04x mask %04x) == %04x? %s after %lu ms\n", data,
775 mask, orig_data, res ? "FAIL" : "PASS",
786 static int process_setup(const char *bus, unsigned char addr,
787 struct mii_setupcmd *setupcmd, unsigned int count)
792 for (k = 0; k < count; ++k) {
793 res = process_setupcmd(bus, addr, &setupcmd[k]);
795 printf("mii cmd %u on bus %s addr %u failed, aborting setup",
796 setupcmd[k].token, bus, addr);
804 static int setup_88e1518(const char *bus, unsigned char addr)
808 res = process_setup(bus, addr,
809 verify_88e1518, ARRAY_SIZE(verify_88e1518));
813 res = process_setup(bus, addr,
814 fixup_88e1518, ARRAY_SIZE(fixup_88e1518));
818 res = process_setup(bus, addr,
819 default_88e1518, ARRAY_SIZE(default_88e1518));
824 res = process_setup(bus, addr,
825 ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518));
830 res = process_setup(bus, addr,
831 swreset_88e1518, ARRAY_SIZE(swreset_88e1518));