3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/ppc4xx-gpio.h>
32 #include <gdsys_fpga.h>
34 #include "../common/osd.h"
36 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
37 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
38 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
39 #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
41 #define LATCH2_MC2_PRESENT_N 0x0080
44 UNITTYPE_VIDEO_USER = 0,
45 UNITTYPE_MAIN_USER = 1,
46 UNITTYPE_VIDEO_SERVER = 2,
47 UNITTYPE_MAIN_SERVER = 3,
80 static unsigned int get_hwver(void)
82 u16 latch3 = in_le16((void *)LATCH3_BASE);
84 return latch3 & 0x0003;
87 static unsigned int get_mc2_present(void)
89 u16 latch2 = in_le16((void *)LATCH2_BASE);
91 return !(latch2 & LATCH2_MC2_PRESENT_N);
94 static void print_fpga_info(unsigned dev)
96 ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
97 u16 versions = in_le16(&fpga->versions);
98 u16 fpga_version = in_le16(&fpga->fpga_version);
99 u16 fpga_features = in_le16(&fpga->fpga_features);
101 unsigned hardware_version;
102 unsigned feature_rs232;
103 unsigned feature_audio;
104 unsigned feature_sysclock;
105 unsigned feature_ramconfig;
106 unsigned feature_carrier_speed;
107 unsigned feature_carriers;
108 unsigned feature_video_channels;
109 int fpga_state = get_fpga_state(dev);
111 printf("FPGA%d: ", dev);
113 hardware_version = versions & 0x000f;
116 && !((hardware_version == HWVER_101)
117 && (fpga_state == FPGA_STATE_DONE_FAILED))) {
118 puts("not available\n");
119 print_fpga_state(dev);
123 unit_type = (versions >> 4) & 0x000f;
124 hardware_version = versions & 0x000f;
125 feature_rs232 = fpga_features & (1<<11);
126 feature_audio = (fpga_features >> 9) & 0x0003;
127 feature_sysclock = (fpga_features >> 7) & 0x0003;
128 feature_ramconfig = (fpga_features >> 5) & 0x0003;
129 feature_carrier_speed = fpga_features & (1<<4);
130 feature_carriers = (fpga_features >> 2) & 0x0003;
131 feature_video_channels = fpga_features & 0x0003;
134 case UNITTYPE_VIDEO_USER:
135 printf("Videochannel Userside");
138 case UNITTYPE_MAIN_USER:
139 printf("Mainchannel Userside");
142 case UNITTYPE_VIDEO_SERVER:
143 printf("Videochannel Serverside");
146 case UNITTYPE_MAIN_SERVER:
147 printf("Mainchannel Serverside");
151 printf("UnitType %d(not supported)", unit_type);
155 switch (hardware_version) {
157 printf(" HW-Ver 1.01\n");
161 printf(" HW-Ver 1.10\n");
165 printf(" HW-Ver %d(not supported)\n",
170 printf(" FPGA V %d.%02d, features:",
171 fpga_version / 100, fpga_version % 100);
173 printf(" %sRS232", feature_rs232 ? "" : "no ");
175 switch (feature_audio) {
177 printf(", no audio");
181 printf(", audio tx");
185 printf(", audio rx");
189 printf(", audio rx+tx");
193 printf(", audio %d(not supported)", feature_audio);
197 switch (feature_sysclock) {
199 printf(", clock 156.25 MHz");
203 printf(", clock %d(not supported)", feature_sysclock);
209 switch (feature_ramconfig) {
215 printf("RAM 32 bit DDR2");
219 printf("RAM 64 bit DDR2");
223 printf("RAM %d(not supported)", feature_ramconfig);
227 printf(", %d carrier(s) %s", feature_carriers,
228 feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
230 printf(", %d video channel(s)\n", feature_video_channels);
234 * Check Board Identity:
238 char *s = getenv("serial#");
242 puts("DLVision 10G");
254 int last_stage_init(void)
256 ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
257 u16 versions = in_le16(&fpga->versions);
260 if (get_mc2_present())
263 if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
266 if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
269 if (get_mc2_present() &&
270 (!get_fpga_state(1) || (get_hwver() == HWVER_101)))
276 void gd405ep_init(void)
280 void gd405ep_set_fpga_reset(unsigned state)
283 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
284 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
286 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
287 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
291 void gd405ep_setup_hw(void)
294 * set "startup-finished"-gpios
296 gpio_write_bit(21, 0);
297 gpio_write_bit(22, 1);
300 int gd405ep_get_fpga_done(unsigned fpga)
302 return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);