3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/processor.h>
12 #include <asm/ppc4xx-gpio.h>
16 #include <gdsys_fpga.h>
18 #include "../common/osd.h"
20 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
21 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
22 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
23 #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
25 #define LATCH2_MC2_PRESENT_N 0x0080
28 UNITTYPE_VIDEO_USER = 0,
29 UNITTYPE_MAIN_USER = 1,
30 UNITTYPE_VIDEO_SERVER = 2,
31 UNITTYPE_MAIN_SERVER = 3,
58 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
68 static unsigned int get_hwver(void)
70 u16 latch3 = in_le16((void *)LATCH3_BASE);
72 return latch3 & 0x0003;
75 static unsigned int get_mc2_present(void)
77 u16 latch2 = in_le16((void *)LATCH2_BASE);
79 return !(latch2 & LATCH2_MC2_PRESENT_N);
82 static void print_fpga_info(unsigned dev)
88 unsigned hardware_version;
89 unsigned feature_rs232;
90 unsigned feature_audio;
91 unsigned feature_sysclock;
92 unsigned feature_ramconfig;
93 unsigned feature_carrier_speed;
94 unsigned feature_carriers;
95 unsigned feature_video_channels;
96 int fpga_state = get_fpga_state(dev);
98 printf("FPGA%d: ", dev);
100 FPGA_GET_REG(dev, versions, &versions);
101 FPGA_GET_REG(dev, fpga_version, &fpga_version);
102 FPGA_GET_REG(dev, fpga_features, &fpga_features);
104 hardware_version = versions & 0x000f;
107 && !((hardware_version == HWVER_101)
108 && (fpga_state == FPGA_STATE_DONE_FAILED))) {
109 puts("not available\n");
110 print_fpga_state(dev);
114 unit_type = (versions >> 4) & 0x000f;
115 hardware_version = versions & 0x000f;
116 feature_rs232 = fpga_features & (1<<11);
117 feature_audio = (fpga_features >> 9) & 0x0003;
118 feature_sysclock = (fpga_features >> 7) & 0x0003;
119 feature_ramconfig = (fpga_features >> 5) & 0x0003;
120 feature_carrier_speed = fpga_features & (1<<4);
121 feature_carriers = (fpga_features >> 2) & 0x0003;
122 feature_video_channels = fpga_features & 0x0003;
125 case UNITTYPE_VIDEO_USER:
126 printf("Videochannel Userside");
129 case UNITTYPE_MAIN_USER:
130 printf("Mainchannel Userside");
133 case UNITTYPE_VIDEO_SERVER:
134 printf("Videochannel Serverside");
137 case UNITTYPE_MAIN_SERVER:
138 printf("Mainchannel Serverside");
142 printf("UnitType %d(not supported)", unit_type);
146 switch (hardware_version) {
148 printf(" HW-Ver 1.01\n");
152 printf(" HW-Ver 1.10-1.12\n");
156 printf(" HW-Ver 1.20\n");
160 printf(" HW-Ver 1.30\n");
164 printf(" HW-Ver %d(not supported)\n",
169 printf(" FPGA V %d.%02d, features:",
170 fpga_version / 100, fpga_version % 100);
172 printf(" %sRS232", feature_rs232 ? "" : "no ");
174 switch (feature_audio) {
176 printf(", no audio");
180 printf(", audio tx");
184 printf(", audio rx");
188 printf(", audio rx+tx");
192 printf(", audio %d(not supported)", feature_audio);
196 switch (feature_sysclock) {
198 printf(", clock 156.25 MHz");
202 printf(", clock %d(not supported)", feature_sysclock);
208 switch (feature_ramconfig) {
214 printf("RAM 32 bit DDR2");
218 printf("RAM 64 bit DDR2");
222 printf("RAM %d(not supported)", feature_ramconfig);
226 printf(", %d carrier(s) %s", feature_carriers,
227 feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
229 printf(", %d video channel(s)\n", feature_video_channels);
233 * Check Board Identity:
237 char *s = getenv("serial#");
241 puts("DLVision 10G");
253 int last_stage_init(void)
257 FPGA_GET_REG(0, versions, &versions);
260 if (get_mc2_present())
263 if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
266 if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
269 if (get_mc2_present() &&
270 (!get_fpga_state(1) || (get_hwver() == HWVER_101)))
276 void gd405ep_init(void)
280 void gd405ep_set_fpga_reset(unsigned state)
283 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
284 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
286 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
287 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
291 void gd405ep_setup_hw(void)
294 * set "startup-finished"-gpios
296 gpio_write_bit(21, 0);
297 gpio_write_bit(22, 1);
300 int gd405ep_get_fpga_done(unsigned fpga)
302 return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);