board/gateworks/gw_ventana/gw_ventana_spl.c

   1 /*
   2  * Copyright (C) 2014 Gateworks Corporation
   3  * Author: Tim Harvey <tharvey@gateworks.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <i2c.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/mx6-ddr.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/imx-common/boot_mode.h>
  17 #include <asm/imx-common/iomux-v3.h>
  18 #include <asm/imx-common/mxc_i2c.h>
  19 #include <spl.h>
  20
  21 #include "ventana_eeprom.h"
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
  26 #define I2C_GSC                 0
  27 #define GSC_EEPROM_ADDR         0x51
  28 #define GSC_EEPROM_DDR_SIZE     0x2B    /* enum (512,1024,2048) MB */
  29 #define GSC_EEPROM_DDR_WIDTH    0x2D    /* enum (32,64) bit */
  30 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  31         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  32         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  33 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  34 #define CONFIG_SYS_I2C_SPEED    100000
  35
  36 /* I2C1: GSC */
  37 static struct i2c_pads_info mx6q_i2c_pad_info0 = {
  38         .scl = {
  39                 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
  40                 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
  41                 .gp = IMX_GPIO_NR(3, 21)
  42         },
  43         .sda = {
  44                 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
  45                 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
  46                 .gp = IMX_GPIO_NR(3, 28)
  47         }
  48 };
  49 static struct i2c_pads_info mx6dl_i2c_pad_info0 = {
  50         .scl = {
  51                 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
  52                 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
  53                 .gp = IMX_GPIO_NR(3, 21)
  54         },
  55         .sda = {
  56                 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
  57                 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
  58                 .gp = IMX_GPIO_NR(3, 28)
  59         }
  60 };
  61
  62 static void i2c_setup_iomux(void)
  63 {
  64         if (is_cpu_type(MXC_CPU_MX6Q))
  65                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
  66         else
  67                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
  68 }
  69
  70 /* configure MX6Q/DUAL mmdc DDR io registers */
  71 struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
  72         /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
  73         .dram_sdclk_0 = 0x00020030,
  74         .dram_sdclk_1 = 0x00020030,
  75         .dram_cas = 0x00020030,
  76         .dram_ras = 0x00020030,
  77         .dram_reset = 0x00020030,
  78         /* SDCKE[0:1]: 100k pull-up */
  79         .dram_sdcke0 = 0x00003000,
  80         .dram_sdcke1 = 0x00003000,
  81         /* SDBA2: pull-up disabled */
  82         .dram_sdba2 = 0x00000000,
  83         /* SDODT[0:1]: 100k pull-up, 40 ohm */
  84         .dram_sdodt0 = 0x00003030,
  85         .dram_sdodt1 = 0x00003030,
  86         /* SDQS[0:7]: Differential input, 40 ohm */
  87         .dram_sdqs0 = 0x00000030,
  88         .dram_sdqs1 = 0x00000030,
  89         .dram_sdqs2 = 0x00000030,
  90         .dram_sdqs3 = 0x00000030,
  91         .dram_sdqs4 = 0x00000030,
  92         .dram_sdqs5 = 0x00000030,
  93         .dram_sdqs6 = 0x00000030,
  94         .dram_sdqs7 = 0x00000030,
  95
  96         /* DQM[0:7]: Differential input, 40 ohm */
  97         .dram_dqm0 = 0x00020030,
  98         .dram_dqm1 = 0x00020030,
  99         .dram_dqm2 = 0x00020030,
 100         .dram_dqm3 = 0x00020030,
 101         .dram_dqm4 = 0x00020030,
 102         .dram_dqm5 = 0x00020030,
 103         .dram_dqm6 = 0x00020030,
 104         .dram_dqm7 = 0x00020030,
 105 };
 106
 107 /* configure MX6Q/DUAL mmdc GRP io registers */
 108 struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
 109         /* DDR3 */
 110         .grp_ddr_type = 0x000c0000,
 111         .grp_ddrmode_ctl = 0x00020000,
 112         /* disable DDR pullups */
 113         .grp_ddrpke = 0x00000000,
 114         /* ADDR[00:16], SDBA[0:1]: 40 ohm */
 115         .grp_addds = 0x00000030,
 116         /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
 117         .grp_ctlds = 0x00000030,
 118         /* DATA[00:63]: Differential input, 40 ohm */
 119         .grp_ddrmode = 0x00020000,
 120         .grp_b0ds = 0x00000030,
 121         .grp_b1ds = 0x00000030,
 122         .grp_b2ds = 0x00000030,
 123         .grp_b3ds = 0x00000030,
 124         .grp_b4ds = 0x00000030,
 125         .grp_b5ds = 0x00000030,
 126         .grp_b6ds = 0x00000030,
 127         .grp_b7ds = 0x00000030,
 128 };
 129
 130 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
 131 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
 132         /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
 133         .dram_sdclk_0 = 0x00020030,
 134         .dram_sdclk_1 = 0x00020030,
 135         .dram_cas = 0x00020030,
 136         .dram_ras = 0x00020030,
 137         .dram_reset = 0x00020030,
 138         /* SDCKE[0:1]: 100k pull-up */
 139         .dram_sdcke0 = 0x00003000,
 140         .dram_sdcke1 = 0x00003000,
 141         /* SDBA2: pull-up disabled */
 142         .dram_sdba2 = 0x00000000,
 143         /* SDODT[0:1]: 100k pull-up, 40 ohm */
 144         .dram_sdodt0 = 0x00003030,
 145         .dram_sdodt1 = 0x00003030,
 146         /* SDQS[0:7]: Differential input, 40 ohm */
 147         .dram_sdqs0 = 0x00000030,
 148         .dram_sdqs1 = 0x00000030,
 149         .dram_sdqs2 = 0x00000030,
 150         .dram_sdqs3 = 0x00000030,
 151         .dram_sdqs4 = 0x00000030,
 152         .dram_sdqs5 = 0x00000030,
 153         .dram_sdqs6 = 0x00000030,
 154         .dram_sdqs7 = 0x00000030,
 155
 156         /* DQM[0:7]: Differential input, 40 ohm */
 157         .dram_dqm0 = 0x00020030,
 158         .dram_dqm1 = 0x00020030,
 159         .dram_dqm2 = 0x00020030,
 160         .dram_dqm3 = 0x00020030,
 161         .dram_dqm4 = 0x00020030,
 162         .dram_dqm5 = 0x00020030,
 163         .dram_dqm6 = 0x00020030,
 164         .dram_dqm7 = 0x00020030,
 165 };
 166
 167 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 168 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 169         /* DDR3 */
 170         .grp_ddr_type = 0x000c0000,
 171         /* SDQS[0:7]: Differential input, 40 ohm */
 172         .grp_ddrmode_ctl = 0x00020000,
 173         /* disable DDR pullups */
 174         .grp_ddrpke = 0x00000000,
 175         /* ADDR[00:16], SDBA[0:1]: 40 ohm */
 176         .grp_addds = 0x00000030,
 177         /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
 178         .grp_ctlds = 0x00000030,
 179         /* DATA[00:63]: Differential input, 40 ohm */
 180         .grp_ddrmode = 0x00020000,
 181         .grp_b0ds = 0x00000030,
 182         .grp_b1ds = 0x00000030,
 183         .grp_b2ds = 0x00000030,
 184         .grp_b3ds = 0x00000030,
 185         .grp_b4ds = 0x00000030,
 186         .grp_b5ds = 0x00000030,
 187         .grp_b6ds = 0x00000030,
 188         .grp_b7ds = 0x00000030,
 189 };
 190
 191 /* MT41K128M16JT-125 (2Gb density) */
 192 static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
 193         .mem_speed = 1600,
 194         .density = 2,
 195         .width = 16,
 196         .banks = 8,
 197         .rowaddr = 14,
 198         .coladdr = 10,
 199         .pagesz = 2,
 200         .trcd = 1375,
 201         .trcmin = 4875,
 202         .trasmin = 3500,
 203 };
 204
 205 /* MT41K256M16HA-125 (4Gb density) */
 206 static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
 207         .mem_speed = 1600,
 208         .density = 4,
 209         .width = 16,
 210         .banks = 8,
 211         .rowaddr = 15,
 212         .coladdr = 10,
 213         .pagesz = 2,
 214         .trcd = 1375,
 215         .trcmin = 4875,
 216         .trasmin = 3500,
 217 };
 218
 219 /*
 220  * calibration - these are the various CPU/DDR3 combinations we support
 221  */
 222
 223 static struct mx6_mmdc_calibration mx6dq_128x16_mmdc_calib = {
 224         /* write leveling calibration determine */
 225         .p0_mpwldectrl0 = 0x00190017,
 226         /* Read DQS Gating calibration */
 227         .p0_mpdgctrl0 = 0x43380347,
 228         /* Read Calibration: DQS delay relative to DQ read access */
 229         .p0_mprddlctl = 0x3C313539,
 230         /* Write Calibration: DQ/DM delay relative to DQS write access */
 231         .p0_mpwrdlctl = 0x36393C39,
 232 };
 233
 234 static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
 235         /* write leveling calibration determine */
 236         .p0_mpwldectrl0 = 0x001B0016,
 237         .p0_mpwldectrl1 = 0x000C000E,
 238         /* Read DQS Gating calibration */
 239         .p0_mpdgctrl0 = 0x4324033A,
 240         .p0_mpdgctrl1 = 0x00000000,
 241         /* Read Calibration: DQS delay relative to DQ read access */
 242         .p0_mprddlctl = 0x40403438,
 243         /* Write Calibration: DQ/DM delay relative to DQS write access */
 244         .p0_mpwrdlctl = 0x40403D36,
 245 };
 246
 247 static struct mx6_mmdc_calibration mx6sdl_128x16_mmdc_calib = {
 248         /* write leveling calibration determine */
 249         .p0_mpwldectrl0 = 0x00190017,
 250         /* Read DQS Gating calibration */
 251         .p0_mpdgctrl0 = 0x43380347,
 252         /* Read Calibration: DQS delay relative to DQ read access */
 253         .p0_mprddlctl = 0x3C313539,
 254         /* Write Calibration: DQ/DM delay relative to DQS write access */
 255         .p0_mpwrdlctl = 0x36393C39,
 256 };
 257
 258 static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = {
 259         /* write leveling calibration determine */
 260         .p0_mpwldectrl0 = 0x00420043,
 261         .p0_mpwldectrl1 = 0x0016001A,
 262         /* Read DQS Gating calibration */
 263         .p0_mpdgctrl0 = 0x4238023B,
 264         .p0_mpdgctrl1 = 0x00000000,
 265         /* Read Calibration: DQS delay relative to DQ read access */
 266         .p0_mprddlctl = 0x40404849,
 267         /* Write Calibration: DQ/DM delay relative to DQS write access */
 268         .p0_mpwrdlctl = 0x40402E2F,
 269 };
 270
 271 static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
 272         /* write leveling calibration determine */
 273         .p0_mpwldectrl0 = 0x00190017,
 274         .p0_mpwldectrl1 = 0x00140026,
 275         /* Read DQS Gating calibration */
 276         .p0_mpdgctrl0 = 0x43380347,
 277         .p0_mpdgctrl1 = 0x433C034D,
 278         /* Read Calibration: DQS delay relative to DQ read access */
 279         .p0_mprddlctl = 0x3C313539,
 280         /* Write Calibration: DQ/DM delay relative to DQS write access */
 281         .p0_mpwrdlctl = 0x36393C39,
 282 };
 283
 284 static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = {
 285         /* write leveling calibration determine */
 286         .p0_mpwldectrl0 = 0x003C003C,
 287         .p0_mpwldectrl1 = 0x001F002A,
 288         /* Read DQS Gating calibration */
 289         .p0_mpdgctrl0 = 0x42410244,
 290         .p0_mpdgctrl1 = 0x4234023A,
 291         /* Read Calibration: DQS delay relative to DQ read access */
 292         .p0_mprddlctl = 0x484A4C4B,
 293         /* Write Calibration: DQ/DM delay relative to DQS write access */
 294         .p0_mpwrdlctl = 0x33342B32,
 295 };
 296
 297 static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = {
 298         /* write leveling calibration determine */
 299         .p0_mpwldectrl0 = 0x00190017,
 300         .p0_mpwldectrl1 = 0x00140026,
 301         .p1_mpwldectrl0 = 0x0021001C,
 302         .p1_mpwldectrl1 = 0x0011001D,
 303         /* Read DQS Gating calibration */
 304         .p0_mpdgctrl0 = 0x43380347,
 305         .p0_mpdgctrl1 = 0x433C034D,
 306         .p1_mpdgctrl0 = 0x032C0324,
 307         .p1_mpdgctrl1 = 0x03310232,
 308         /* Read Calibration: DQS delay relative to DQ read access */
 309         .p0_mprddlctl = 0x3C313539,
 310         .p1_mprddlctl = 0x37343141,
 311         /* Write Calibration: DQ/DM delay relative to DQS write access */
 312         .p0_mpwrdlctl = 0x36393C39,
 313         .p1_mpwrdlctl = 0x42344438,
 314 };
 315
 316 static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = {
 317         /* write leveling calibration determine */
 318         .p0_mpwldectrl0 = 0x003C003C,
 319         .p0_mpwldectrl1 = 0x001F002A,
 320         .p1_mpwldectrl0 = 0x00330038,
 321         .p1_mpwldectrl1 = 0x0022003F,
 322         /* Read DQS Gating calibration */
 323         .p0_mpdgctrl0 = 0x42410244,
 324         .p0_mpdgctrl1 = 0x4234023A,
 325         .p1_mpdgctrl0 = 0x022D022D,
 326         .p1_mpdgctrl1 = 0x021C0228,
 327         /* Read Calibration: DQS delay relative to DQ read access */
 328         .p0_mprddlctl = 0x484A4C4B,
 329         .p1_mprddlctl = 0x4B4D4E4B,
 330         /* Write Calibration: DQ/DM delay relative to DQS write access */
 331         .p0_mpwrdlctl = 0x33342B32,
 332         .p1_mpwrdlctl = 0x3933332B,
 333 };
 334
 335 static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
 336         /* write leveling calibration determine */
 337         .p0_mpwldectrl0 = 0x001E001A,
 338         .p0_mpwldectrl1 = 0x0026001F,
 339         /* Read DQS Gating calibration */
 340         .p0_mpdgctrl0 = 0x43370349,
 341         .p0_mpdgctrl1 = 0x032D0327,
 342         /* Read Calibration: DQS delay relative to DQ read access */
 343         .p0_mprddlctl = 0x3D303639,
 344         /* Write Calibration: DQ/DM delay relative to DQS write access */
 345         .p0_mpwrdlctl = 0x32363934,
 346 };
 347
 348 static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = {
 349         /* write leveling calibration determine */
 350         .p0_mpwldectrl0 = 0X00480047,
 351         .p0_mpwldectrl1 = 0X003D003F,
 352         /* Read DQS Gating calibration */
 353         .p0_mpdgctrl0 = 0X423E0241,
 354         .p0_mpdgctrl1 = 0X022B022C,
 355         /* Read Calibration: DQS delay relative to DQ read access */
 356         .p0_mprddlctl = 0X49454A4A,
 357         /* Write Calibration: DQ/DM delay relative to DQS write access */
 358         .p0_mpwrdlctl = 0X2E372C32,
 359 };
 360
 361 static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
 362         /* write leveling calibration determine */
 363         .p0_mpwldectrl0 = 0X00220021,
 364         .p0_mpwldectrl1 = 0X00200030,
 365         .p1_mpwldectrl0 = 0X002D0027,
 366         .p1_mpwldectrl1 = 0X00150026,
 367         /* Read DQS Gating calibration */
 368         .p0_mpdgctrl0 = 0x43330342,
 369         .p0_mpdgctrl1 = 0x0339034A,
 370         .p1_mpdgctrl0 = 0x032F0325,
 371         .p1_mpdgctrl1 = 0x032F022E,
 372         /* Read Calibration: DQS delay relative to DQ read access */
 373         .p0_mprddlctl = 0X3A2E3437,
 374         .p1_mprddlctl = 0X35312F3F,
 375         /* Write Calibration: DQ/DM delay relative to DQS write access */
 376         .p0_mpwrdlctl = 0X33363B37,
 377         .p1_mpwrdlctl = 0X40304239,
 378 };
 379
 380 static void spl_dram_init(int width, int size_mb, int board_model)
 381 {
 382         struct mx6_ddr3_cfg *mem = NULL;
 383         struct mx6_mmdc_calibration *calib = NULL;
 384         struct mx6_ddr_sysinfo sysinfo = {
 385                 /* width of data bus:0=16,1=32,2=64 */
 386                 .dsize = width/32,
 387                 /* config for full 4GB range so that get_mem_size() works */
 388                 .cs_density = 32, /* 32Gb per CS */
 389                 /* single chip select */
 390                 .ncs = 1,
 391                 .cs1_mirror = 0,
 392                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 393 #ifdef RTT_NOM_120OHM
 394                 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/,      /* RTT_Nom = RZQ/2 */
 395 #else
 396                 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
 397 #endif
 398                 .walat = 1,     /* Write additional latency */
 399                 .ralat = 5,     /* Read additional latency */
 400                 .mif3_mode = 3, /* Command prediction working mode */
 401                 .bi_on = 1,     /* Bank interleaving enabled */
 402                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 403                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 404                 .pd_fast_exit = 1, /* enable precharge power-down fast exit */
 405         };
 406
 407         /*
 408          * MMDC Calibration requires the following data:
 409          *   mx6_mmdc_calibration - board-specific calibration (routing delays)
 410          *      these calibration values depend on board routing, SoC, and DDR
 411          *   mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
 412          *   mx6_ddr_cfg - chip specific timing/layout details
 413          */
 414         if (width == 16 && size_mb == 256) {
 415                 mem = &mt41k128m16jt_125;
 416                 if (is_cpu_type(MXC_CPU_MX6Q))
 417                         calib = &mx6dq_128x16_mmdc_calib;
 418                 else
 419                         calib = &mx6sdl_128x16_mmdc_calib;
 420                 debug("2gB density\n");
 421         } else if (width == 16 && size_mb == 512) {
 422                 mem = &mt41k256m16ha_125;
 423                 if (is_cpu_type(MXC_CPU_MX6Q))
 424                         calib = &mx6dq_256x16_mmdc_calib;
 425                 else
 426                         calib = &mx6sdl_256x16_mmdc_calib;
 427                 debug("4gB density\n");
 428         } else if (width == 32 && size_mb == 512) {
 429                 mem = &mt41k128m16jt_125;
 430                 if (is_cpu_type(MXC_CPU_MX6Q))
 431                         calib = &mx6dq_128x32_mmdc_calib;
 432                 else
 433                         calib = &mx6sdl_128x32_mmdc_calib;
 434                 debug("2gB density\n");
 435         } else if (width == 64 && size_mb == 1024) {
 436                 mem = &mt41k128m16jt_125;
 437                 if (is_cpu_type(MXC_CPU_MX6Q))
 438                         calib = &mx6dq_128x64_mmdc_calib;
 439                 else
 440                         calib = &mx6sdl_128x64_mmdc_calib;
 441                 debug("2gB density\n");
 442         } else if (width == 32 && size_mb == 1024) {
 443                 mem = &mt41k256m16ha_125;
 444                 if (is_cpu_type(MXC_CPU_MX6Q))
 445                         calib = &mx6dq_256x32_mmdc_calib;
 446                 else
 447                         calib = &mx6sdl_256x32_mmdc_calib;
 448                 debug("4gB density\n");
 449         } else if (width == 64 && size_mb == 2048) {
 450                 mem = &mt41k256m16ha_125;
 451                 if (is_cpu_type(MXC_CPU_MX6Q))
 452                         calib = &mx6dq_256x64_mmdc_calib;
 453                 debug("4gB density\n");
 454         }
 455
 456         if (!mem) {
 457                 puts("Error: Invalid Memory Configuration\n");
 458                 hang();
 459         }
 460         if (!calib) {
 461                 puts("Error: Invalid Board Calibration Configuration\n");
 462                 hang();
 463         }
 464
 465         if (is_cpu_type(MXC_CPU_MX6Q))
 466                 mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs,
 467                                  &mx6dq_grp_ioregs);
 468         else
 469                 mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs,
 470                                   &mx6sdl_grp_ioregs);
 471         mx6_dram_cfg(&sysinfo, calib, mem);
 472 }
 473
 474 static void ccgr_init(void)
 475 {
 476         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 477
 478         writel(0x00C03F3F, &ccm->CCGR0);
 479         writel(0x0030FC03, &ccm->CCGR1);
 480         writel(0x0FFFC000, &ccm->CCGR2);
 481         writel(0x3FF00000, &ccm->CCGR3);
 482         writel(0xFFFFF300, &ccm->CCGR4);        /* enable NAND/GPMI/BCH clks */
 483         writel(0x0F0000C3, &ccm->CCGR5);
 484         writel(0x000003FF, &ccm->CCGR6);
 485 }
 486
 487 static void gpr_init(void)
 488 {
 489         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 490
 491         /* enable AXI cache for VDOA/VPU/IPU */
 492         writel(0xF00000CF, &iomux->gpr[4]);
 493         /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
 494         writel(0x007F007F, &iomux->gpr[6]);
 495         writel(0x007F007F, &iomux->gpr[7]);
 496 }
 497
 498 /*
 499  * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
 500  * - we have a stack and a place to store GD, both in SRAM
 501  * - no variable global data is available
 502  */
 503 void board_init_f(ulong dummy)
 504 {
 505         struct ventana_board_info ventana_info;
 506         int board_model;
 507
 508         /* setup AIPS and disable watchdog */
 509         arch_cpu_init();
 510
 511         ccgr_init();
 512         gpr_init();
 513
 514         /* iomux and setup of i2c */
 515         board_early_init_f();
 516         i2c_setup_iomux();
 517
 518         /* setup GP timer */
 519         timer_init();
 520
 521         /* UART clocks enabled and gd valid - init serial console */
 522         preloader_console_init();
 523
 524         /* read/validate EEPROM info to determine board model and SDRAM cfg */
 525         board_model = read_eeprom(I2C_GSC, &ventana_info);
 526
 527         /* provide some some default: 32bit 128MB */
 528         if (GW_UNKNOWN == board_model) {
 529                 ventana_info.sdram_width = 2;
 530                 ventana_info.sdram_size = 3;
 531         }
 532
 533         /* configure MMDC for SDRAM width/size and per-model calibration */
 534         spl_dram_init(8 << ventana_info.sdram_width,
 535                       16 << ventana_info.sdram_size,
 536                       board_model);
 537
 538         /* Clear the BSS. */
 539         memset(__bss_start, 0, __bss_end - __bss_start);
 540
 541         /* load/boot image from boot device */
 542         board_init_r(NULL, 0);
 543 }
 544
 545 void reset_cpu(ulong addr)
 546 {
 547 }