board/gateworks/gw_ventana/gw_ventana.c

   1 /*
   2  * Copyright (C) 2013 Gateworks Corporation
   3  *
   4  * Author: Tim Harvey <tharvey@gateworks.com>
   5  *
   6  * SPDX-License-Identifier: GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/mxc_hdmi.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/gpio.h>
  19 #include <asm/imx-common/iomux-v3.h>
  20 #include <asm/imx-common/mxc_i2c.h>
  21 #include <asm/imx-common/boot_mode.h>
  22 #include <asm/imx-common/sata.h>
  23 #include <asm/imx-common/spi.h>
  24 #include <asm/imx-common/video.h>
  25 #include <dm/platform_data/serial_mxc.h>
  26 #include <jffs2/load_kernel.h>
  27 #include <hwconfig.h>
  28 #include <i2c.h>
  29 #include <linux/ctype.h>
  30 #include <fdt_support.h>
  31 #include <fsl_esdhc.h>
  32 #include <miiphy.h>
  33 #include <mmc.h>
  34 #include <mtd_node.h>
  35 #include <netdev.h>
  36 #include <pci.h>
  37 #include <power/pmic.h>
  38 #include <power/ltc3676_pmic.h>
  39 #include <power/pfuze100_pmic.h>
  40 #include <fdt_support.h>
  41 #include <jffs2/load_kernel.h>
  42 #include <spi_flash.h>
  43
  44 #include "gsc.h"
  45 #include "ventana_eeprom.h"
  46
  47 DECLARE_GLOBAL_DATA_PTR;
  48
  49 /* GPIO's common to all baseboards */
  50 #define GP_PHY_RST      IMX_GPIO_NR(1, 30)
  51 #define GP_USB_OTG_PWR  IMX_GPIO_NR(3, 22)
  52 #define GP_SD3_CD       IMX_GPIO_NR(7, 0)
  53 #define GP_RS232_EN     IMX_GPIO_NR(2, 11)
  54 #define GP_MSATA_SEL    IMX_GPIO_NR(2, 8)
  55
  56 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  57         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  58         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  59
  60 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  61         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
  62         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  63
  64 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  65         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  66         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  67
  68 #define SPI_PAD_CTRL (PAD_CTL_HYS |                             \
  69         PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
  70         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  71
  72 #define DIO_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |              \
  73         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  74         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  75
  76 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  77         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  78         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  79
  80 #define IRQ_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |              \
  81         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  82         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  83
  84 #define DIO_PAD_CFG   (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION)
  85
  86
  87 /*
  88  * EEPROM board info struct populated by read_eeprom so that we only have to
  89  * read it once.
  90  */
  91 struct ventana_board_info ventana_info;
  92
  93 static int board_type;
  94
  95 /* UART1: Function varies per baseboard */
  96 static iomux_v3_cfg_t const uart1_pads[] = {
  97         IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  98         IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  99 };
 100
 101 /* UART2: Serial Console */
 102 static iomux_v3_cfg_t const uart2_pads[] = {
 103         IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 104         IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 105 };
 106
 107 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 108
 109 /* I2C1: GSC */
 110 static struct i2c_pads_info mx6q_i2c_pad_info0 = {
 111         .scl = {
 112                 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
 113                 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
 114                 .gp = IMX_GPIO_NR(3, 21)
 115         },
 116         .sda = {
 117                 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
 118                 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
 119                 .gp = IMX_GPIO_NR(3, 28)
 120         }
 121 };
 122 static struct i2c_pads_info mx6dl_i2c_pad_info0 = {
 123         .scl = {
 124                 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
 125                 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
 126                 .gp = IMX_GPIO_NR(3, 21)
 127         },
 128         .sda = {
 129                 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
 130                 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
 131                 .gp = IMX_GPIO_NR(3, 28)
 132         }
 133 };
 134
 135 /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
 136 static struct i2c_pads_info mx6q_i2c_pad_info1 = {
 137         .scl = {
 138                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
 139                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
 140                 .gp = IMX_GPIO_NR(4, 12)
 141         },
 142         .sda = {
 143                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
 144                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 145                 .gp = IMX_GPIO_NR(4, 13)
 146         }
 147 };
 148 static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
 149         .scl = {
 150                 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
 151                 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
 152                 .gp = IMX_GPIO_NR(4, 12)
 153         },
 154         .sda = {
 155                 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
 156                 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 157                 .gp = IMX_GPIO_NR(4, 13)
 158         }
 159 };
 160
 161 /* I2C3: Misc/Expansion */
 162 static struct i2c_pads_info mx6q_i2c_pad_info2 = {
 163         .scl = {
 164                 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
 165                 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
 166                 .gp = IMX_GPIO_NR(1, 3)
 167         },
 168         .sda = {
 169                 .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
 170                 .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
 171                 .gp = IMX_GPIO_NR(1, 6)
 172         }
 173 };
 174 static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
 175         .scl = {
 176                 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
 177                 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
 178                 .gp = IMX_GPIO_NR(1, 3)
 179         },
 180         .sda = {
 181                 .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
 182                 .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
 183                 .gp = IMX_GPIO_NR(1, 6)
 184         }
 185 };
 186
 187 /* MMC */
 188 static iomux_v3_cfg_t const usdhc3_pads[] = {
 189         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 190         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 191         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 192         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 193         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 194         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 195         /* CD */
 196         IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00  | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 197 };
 198
 199 /* ENET */
 200 static iomux_v3_cfg_t const enet_pads[] = {
 201         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 202         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 203         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 204         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 205         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 206         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 207         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 208         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
 209                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 210         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
 211                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 212         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 213         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 214         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 215         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 216         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 217         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
 218                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 219         /* PHY nRST */
 220         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
 221 };
 222
 223 /* NAND */
 224 static iomux_v3_cfg_t const nfc_pads[] = {
 225         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 226         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 227         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 228         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 229         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 230         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 231         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 232         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 233         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 234         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 235         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 236         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 237         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 238         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 239         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 240 };
 241
 242 #ifdef CONFIG_CMD_NAND
 243 static void setup_gpmi_nand(void)
 244 {
 245         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 246
 247         /* config gpmi nand iomux */
 248         SETUP_IOMUX_PADS(nfc_pads);
 249
 250         /* config gpmi and bch clock to 100 MHz */
 251         clrsetbits_le32(&mxc_ccm->cs2cdr,
 252                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 253                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 254                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 255                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 256                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 257                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 258
 259         /* enable gpmi and bch clock gating */
 260         setbits_le32(&mxc_ccm->CCGR4,
 261                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 262                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 263                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 264                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 265                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 266
 267         /* enable apbh clock gating */
 268         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 269 }
 270 #endif
 271
 272 static void setup_iomux_enet(int gpio)
 273 {
 274         SETUP_IOMUX_PADS(enet_pads);
 275
 276         /* toggle PHY_RST# */
 277         gpio_request(gpio, "phy_rst#");
 278         gpio_direction_output(gpio, 0);
 279         mdelay(2);
 280         gpio_set_value(gpio, 1);
 281 }
 282
 283 static void setup_iomux_uart(void)
 284 {
 285         SETUP_IOMUX_PADS(uart1_pads);
 286         SETUP_IOMUX_PADS(uart2_pads);
 287 }
 288
 289 #ifdef CONFIG_USB_EHCI_MX6
 290 static iomux_v3_cfg_t const usb_pads[] = {
 291         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID   | DIO_PAD_CFG),
 292         IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
 293         /* OTG PWR */
 294         IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22  | DIO_PAD_CFG),
 295 };
 296
 297 int board_ehci_hcd_init(int port)
 298 {
 299         struct ventana_board_info *info = &ventana_info;
 300         int gpio;
 301
 302         SETUP_IOMUX_PADS(usb_pads);
 303
 304         /* Reset USB HUB (present on GW54xx/GW53xx) */
 305         switch (info->model[3]) {
 306         case '3': /* GW53xx */
 307         case '5': /* GW552x */
 308                 SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG);
 309                 gpio = (IMX_GPIO_NR(1, 9));
 310                 break;
 311         case '4': /* GW54xx */
 312                 SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG);
 313                 gpio = (IMX_GPIO_NR(1, 16));
 314                 break;
 315         default:
 316                 return 0;
 317         }
 318
 319         /* request and toggle hub rst */
 320         gpio_request(gpio, "usb_hub_rst#");
 321         gpio_direction_output(gpio, 0);
 322         mdelay(2);
 323         gpio_set_value(gpio, 1);
 324
 325         return 0;
 326 }
 327
 328 int board_ehci_power(int port, int on)
 329 {
 330         if (port)
 331                 return 0;
 332         gpio_request(GP_USB_OTG_PWR, "usb_otg_pwr");
 333         gpio_set_value(GP_USB_OTG_PWR, on);
 334         return 0;
 335 }
 336 #endif /* CONFIG_USB_EHCI_MX6 */
 337
 338 #ifdef CONFIG_FSL_ESDHC
 339 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
 340
 341 int board_mmc_getcd(struct mmc *mmc)
 342 {
 343         /* Card Detect */
 344         gpio_request(GP_SD3_CD, "sd_cd");
 345         gpio_direction_input(GP_SD3_CD);
 346         return !gpio_get_value(GP_SD3_CD);
 347 }
 348
 349 int board_mmc_init(bd_t *bis)
 350 {
 351         /* Only one USDHC controller on Ventana */
 352         SETUP_IOMUX_PADS(usdhc3_pads);
 353         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 354         usdhc_cfg.max_bus_width = 4;
 355
 356         return fsl_esdhc_initialize(bis, &usdhc_cfg);
 357 }
 358 #endif /* CONFIG_FSL_ESDHC */
 359
 360 #ifdef CONFIG_MXC_SPI
 361 iomux_v3_cfg_t const ecspi1_pads[] = {
 362         /* SS1 */
 363         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 364         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 365         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 366         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 367 };
 368
 369 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 370 {
 371         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
 372 }
 373
 374 static void setup_spi(void)
 375 {
 376         gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
 377         gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
 378         SETUP_IOMUX_PADS(ecspi1_pads);
 379 }
 380 #endif
 381
 382 /* configure eth0 PHY board-specific LED behavior */
 383 int board_phy_config(struct phy_device *phydev)
 384 {
 385         unsigned short val;
 386
 387         /* Marvel 88E1510 */
 388         if (phydev->phy_id == 0x1410dd1) {
 389                 /*
 390                  * Page 3, Register 16: LED[2:0] Function Control Register
 391                  * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
 392                  * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
 393                  */
 394                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
 395                 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
 396                 val &= 0xff00;
 397                 val |= 0x0017;
 398                 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
 399                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 400         }
 401
 402         if (phydev->drv->config)
 403                 phydev->drv->config(phydev);
 404
 405         return 0;
 406 }
 407
 408 int board_eth_init(bd_t *bis)
 409 {
 410 #ifdef CONFIG_FEC_MXC
 411         if (board_type != GW551x && board_type != GW552x) {
 412                 setup_iomux_enet(GP_PHY_RST);
 413                 cpu_eth_init(bis);
 414         }
 415 #endif
 416
 417 #ifdef CONFIG_E1000
 418         e1000_initialize(bis);
 419 #endif
 420
 421 #ifdef CONFIG_CI_UDC
 422         /* For otg ethernet*/
 423         usb_eth_initialize(bis);
 424 #endif
 425
 426         /* default to the first detected enet dev */
 427         if (!getenv("ethprime")) {
 428                 struct eth_device *dev = eth_get_dev_by_index(0);
 429                 if (dev) {
 430                         setenv("ethprime", dev->name);
 431                         printf("set ethprime to %s\n", getenv("ethprime"));
 432                 }
 433         }
 434
 435         return 0;
 436 }
 437
 438 #if defined(CONFIG_VIDEO_IPUV3)
 439
 440 static void enable_hdmi(struct display_info_t const *dev)
 441 {
 442         imx_enable_hdmi_phy();
 443 }
 444
 445 static int detect_i2c(struct display_info_t const *dev)
 446 {
 447         return i2c_set_bus_num(dev->bus) == 0 &&
 448                 i2c_probe(dev->addr) == 0;
 449 }
 450
 451 static void enable_lvds(struct display_info_t const *dev)
 452 {
 453         struct iomuxc *iomux = (struct iomuxc *)
 454                                 IOMUXC_BASE_ADDR;
 455
 456         /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
 457         u32 reg = readl(&iomux->gpr[2]);
 458         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 459         writel(reg, &iomux->gpr[2]);
 460
 461         /* Enable Backlight */
 462         gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
 463         SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
 464         gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
 465 }
 466
 467 struct display_info_t const displays[] = {{
 468         /* HDMI Output */
 469         .bus    = -1,
 470         .addr   = 0,
 471         .pixfmt = IPU_PIX_FMT_RGB24,
 472         .detect = detect_hdmi,
 473         .enable = enable_hdmi,
 474         .mode   = {
 475                 .name           = "HDMI",
 476                 .refresh        = 60,
 477                 .xres           = 1024,
 478                 .yres           = 768,
 479                 .pixclock       = 15385,
 480                 .left_margin    = 220,
 481                 .right_margin   = 40,
 482                 .upper_margin   = 21,
 483                 .lower_margin   = 7,
 484                 .hsync_len      = 60,
 485                 .vsync_len      = 10,
 486                 .sync           = FB_SYNC_EXT,
 487                 .vmode          = FB_VMODE_NONINTERLACED
 488 } }, {
 489         /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
 490         .bus    = 2,
 491         .addr   = 0x4,
 492         .pixfmt = IPU_PIX_FMT_LVDS666,
 493         .detect = detect_i2c,
 494         .enable = enable_lvds,
 495         .mode   = {
 496                 .name           = "Hannstar-XGA",
 497                 .refresh        = 60,
 498                 .xres           = 1024,
 499                 .yres           = 768,
 500                 .pixclock       = 15385,
 501                 .left_margin    = 220,
 502                 .right_margin   = 40,
 503                 .upper_margin   = 21,
 504                 .lower_margin   = 7,
 505                 .hsync_len      = 60,
 506                 .vsync_len      = 10,
 507                 .sync           = FB_SYNC_EXT,
 508                 .vmode          = FB_VMODE_NONINTERLACED
 509 } }, {
 510         /* DLC700JMG-T-4 */
 511         .bus    = 0,
 512         .addr   = 0,
 513         .detect = NULL,
 514         .enable = enable_lvds,
 515         .pixfmt = IPU_PIX_FMT_LVDS666,
 516         .mode   = {
 517                 .name           = "DLC700JMGT4",
 518                 .refresh        = 60,
 519                 .xres           = 1024,         /* 1024x600active pixels */
 520                 .yres           = 600,
 521                 .pixclock       = 15385,        /* 64MHz */
 522                 .left_margin    = 220,
 523                 .right_margin   = 40,
 524                 .upper_margin   = 21,
 525                 .lower_margin   = 7,
 526                 .hsync_len      = 60,
 527                 .vsync_len      = 10,
 528                 .sync           = FB_SYNC_EXT,
 529                 .vmode          = FB_VMODE_NONINTERLACED
 530 } }, {
 531         /* DLC800FIG-T-3 */
 532         .bus    = 0,
 533         .addr   = 0,
 534         .detect = NULL,
 535         .enable = enable_lvds,
 536         .pixfmt = IPU_PIX_FMT_LVDS666,
 537         .mode   = {
 538                 .name           = "DLC800FIGT3",
 539                 .refresh        = 60,
 540                 .xres           = 1024,         /* 1024x768 active pixels */
 541                 .yres           = 768,
 542                 .pixclock       = 15385,        /* 64MHz */
 543                 .left_margin    = 220,
 544                 .right_margin   = 40,
 545                 .upper_margin   = 21,
 546                 .lower_margin   = 7,
 547                 .hsync_len      = 60,
 548                 .vsync_len      = 10,
 549                 .sync           = FB_SYNC_EXT,
 550                 .vmode          = FB_VMODE_NONINTERLACED
 551 } } };
 552 size_t display_count = ARRAY_SIZE(displays);
 553
 554 static void setup_display(void)
 555 {
 556         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 557         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 558         int reg;
 559
 560         enable_ipu_clock();
 561         imx_setup_hdmi();
 562         /* Turn on LDB0,IPU,IPU DI0 clocks */
 563         reg = __raw_readl(&mxc_ccm->CCGR3);
 564         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 565         writel(reg, &mxc_ccm->CCGR3);
 566
 567         /* set LDB0, LDB1 clk select to 011/011 */
 568         reg = readl(&mxc_ccm->cs2cdr);
 569         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 570                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 571         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 572               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 573         writel(reg, &mxc_ccm->cs2cdr);
 574
 575         reg = readl(&mxc_ccm->cscmr2);
 576         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 577         writel(reg, &mxc_ccm->cscmr2);
 578
 579         reg = readl(&mxc_ccm->chsccdr);
 580         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 581                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 582         writel(reg, &mxc_ccm->chsccdr);
 583
 584         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 585              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 586              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 587              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 588              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 589              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 590              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 591              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 592              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 593         writel(reg, &iomux->gpr[2]);
 594
 595         reg = readl(&iomux->gpr[3]);
 596         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 597             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 598                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 599         writel(reg, &iomux->gpr[3]);
 600
 601         /* Backlight CABEN on LVDS connector */
 602         gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
 603         SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
 604         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 605 }
 606 #endif /* CONFIG_VIDEO_IPUV3 */
 607
 608 /*
 609  * Baseboard specific GPIO
 610  */
 611
 612 /* common to add baseboards */
 613 static iomux_v3_cfg_t const gw_gpio_pads[] = {
 614         /* MSATA_EN */
 615         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
 616         /* RS232_EN# */
 617         IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
 618 };
 619
 620 /* prototype */
 621 static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
 622         /* PANLEDG# */
 623         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 624         /* PANLEDR# */
 625         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 626         /* LOCLED# */
 627         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 628         /* RS485_EN */
 629         IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
 630         /* IOEXP_PWREN# */
 631         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 632         /* IOEXP_IRQ# */
 633         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 634         /* VID_EN */
 635         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 636         /* DIOI2C_DIS# */
 637         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 638         /* PCICK_SSON */
 639         IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
 640         /* PCI_RST# */
 641         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 642 };
 643
 644 static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
 645         /* PANLEDG# */
 646         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 647         /* PANLEDR# */
 648         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 649         /* IOEXP_PWREN# */
 650         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 651         /* IOEXP_IRQ# */
 652         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 653
 654         /* GPS_SHDN */
 655         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 656         /* VID_PWR */
 657         IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
 658         /* PCI_RST# */
 659         IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
 660         /* PCIESKT_WDIS# */
 661         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 662 };
 663
 664 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
 665         /* PANLEDG# */
 666         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 667         /* PANLEDR# */
 668         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 669         /* IOEXP_PWREN# */
 670         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 671         /* IOEXP_IRQ# */
 672         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 673
 674         /* MX6_LOCLED# */
 675         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 676         /* GPS_SHDN */
 677         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
 678         /* USBOTG_SEL */
 679         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 680         /* VID_PWR */
 681         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 682         /* PCI_RST# */
 683         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 684         /* PCI_RST# (GW522x) */
 685         IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG),
 686         /* PCIESKT_WDIS# */
 687         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 688 };
 689
 690 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
 691         /* PANLEDG# */
 692         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 693         /* PANLEDR# */
 694         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 695         /* MX6_LOCLED# */
 696         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 697         /* IOEXP_PWREN# */
 698         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 699         /* IOEXP_IRQ# */
 700         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 701         /* DIOI2C_DIS# */
 702         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 703         /* GPS_SHDN */
 704         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
 705         /* VID_EN */
 706         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 707         /* PCI_RST# */
 708         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 709         /* PCIESKT_WDIS# */
 710         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 711 };
 712
 713 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
 714         /* PANLEDG# */
 715         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 716         /* PANLEDR# */
 717         IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
 718         /* MX6_LOCLED# */
 719         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 720         /* MIPI_DIO */
 721         IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG),
 722         /* RS485_EN */
 723         IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG),
 724         /* IOEXP_PWREN# */
 725         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 726         /* IOEXP_IRQ# */
 727         IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 728         /* DIOI2C_DIS# */
 729         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 730         /* PCI_RST# */
 731         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 732         /* VID_EN */
 733         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 734         /* PCIESKT_WDIS# */
 735         IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
 736 };
 737
 738 static iomux_v3_cfg_t const gw551x_gpio_pads[] = {
 739         /* PANLED# */
 740         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 741         /* PCI_RST# */
 742         IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
 743         /* PCIESKT_WDIS# */
 744         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 745 };
 746
 747 static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
 748         /* PANLEDG# */
 749         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 750         /* PANLEDR# */
 751         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 752         /* MX6_LOCLED# */
 753         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 754         /* PCI_RST# */
 755         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 756         /* MX6_DIO[4:9] */
 757         IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG),
 758         IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
 759         IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG),
 760         IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG),
 761         IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG),
 762         IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG),
 763         /* PCIEGBE1_OFF# */
 764         IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
 765         /* PCIEGBE2_OFF# */
 766         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 767         /* PCIESKT_WDIS# */
 768         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 769 };
 770
 771 /*
 772  * each baseboard has 4 user configurable Digital IO lines which can
 773  * be pinmuxed as a GPIO or in some cases a PWM
 774  */
 775 struct dio_cfg {
 776         iomux_v3_cfg_t gpio_padmux[2];
 777         unsigned gpio_param;
 778         iomux_v3_cfg_t pwm_padmux[2];
 779         unsigned pwm_param;
 780 };
 781
 782 struct ventana {
 783         /* pinmux */
 784         iomux_v3_cfg_t const *gpio_pads;
 785         int num_pads;
 786         /* DIO pinmux/val */
 787         struct dio_cfg dio_cfg[4];
 788         int num_gpios;
 789         /* various gpios (0 if non-existent) */
 790         int leds[3];
 791         int pcie_rst;
 792         int mezz_pwren;
 793         int mezz_irq;
 794         int rs485en;
 795         int gps_shdn;
 796         int vidin_en;
 797         int dioi2c_en;
 798         int pcie_sson;
 799         int usb_sel;
 800         int wdis;
 801 };
 802
 803 static struct ventana gpio_cfg[] = {
 804         /* GW5400proto */
 805         {
 806                 .gpio_pads = gw54xx_gpio_pads,
 807                 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
 808                 .dio_cfg = {
 809                         {
 810                                 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
 811                                 IMX_GPIO_NR(1, 9),
 812                                 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
 813                                 1
 814                         },
 815                         {
 816                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 817                                 IMX_GPIO_NR(1, 19),
 818                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 819                                 2
 820                         },
 821                         {
 822                                 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
 823                                 IMX_GPIO_NR(2, 9),
 824                                 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
 825                                 3
 826                         },
 827                         {
 828                                 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
 829                                 IMX_GPIO_NR(2, 10),
 830                                 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
 831                                 4
 832                         },
 833                 },
 834                 .num_gpios = 4,
 835                 .leds = {
 836                         IMX_GPIO_NR(4, 6),
 837                         IMX_GPIO_NR(4, 10),
 838                         IMX_GPIO_NR(4, 15),
 839                 },
 840                 .pcie_rst = IMX_GPIO_NR(1, 29),
 841                 .mezz_pwren = IMX_GPIO_NR(4, 7),
 842                 .mezz_irq = IMX_GPIO_NR(4, 9),
 843                 .rs485en = IMX_GPIO_NR(3, 24),
 844                 .dioi2c_en = IMX_GPIO_NR(4,  5),
 845                 .pcie_sson = IMX_GPIO_NR(1, 20),
 846         },
 847
 848         /* GW51xx */
 849         {
 850                 .gpio_pads = gw51xx_gpio_pads,
 851                 .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
 852                 .dio_cfg = {
 853                         {
 854                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 855                                 IMX_GPIO_NR(1, 16),
 856                                 { 0, 0 },
 857                                 0
 858                         },
 859                         {
 860                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 861                                 IMX_GPIO_NR(1, 19),
 862                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 863                                 2
 864                         },
 865                         {
 866                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 867                                 IMX_GPIO_NR(1, 17),
 868                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 869                                 3
 870                         },
 871                         {
 872                                 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
 873                                 IMX_GPIO_NR(1, 18),
 874                                 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
 875                                 4
 876                         },
 877                 },
 878                 .num_gpios = 4,
 879                 .leds = {
 880                         IMX_GPIO_NR(4, 6),
 881                         IMX_GPIO_NR(4, 10),
 882                 },
 883                 .pcie_rst = IMX_GPIO_NR(1, 0),
 884                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 885                 .mezz_irq = IMX_GPIO_NR(2, 18),
 886                 .gps_shdn = IMX_GPIO_NR(1, 2),
 887                 .vidin_en = IMX_GPIO_NR(5, 20),
 888                 .wdis = IMX_GPIO_NR(7, 12),
 889         },
 890
 891         /* GW52xx */
 892         {
 893                 .gpio_pads = gw52xx_gpio_pads,
 894                 .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
 895                 .dio_cfg = {
 896                         {
 897                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 898                                 IMX_GPIO_NR(1, 16),
 899                                 { 0, 0 },
 900                                 0
 901                         },
 902                         {
 903                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 904                                 IMX_GPIO_NR(1, 19),
 905                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 906                                 2
 907                         },
 908                         {
 909                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 910                                 IMX_GPIO_NR(1, 17),
 911                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 912                                 3
 913                         },
 914                         {
 915                                 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
 916                                 IMX_GPIO_NR(1, 20),
 917                                 { 0, 0 },
 918                                 0
 919                         },
 920                 },
 921                 .num_gpios = 4,
 922                 .leds = {
 923                         IMX_GPIO_NR(4, 6),
 924                         IMX_GPIO_NR(4, 7),
 925                         IMX_GPIO_NR(4, 15),
 926                 },
 927                 .pcie_rst = IMX_GPIO_NR(1, 29),
 928                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 929                 .mezz_irq = IMX_GPIO_NR(2, 18),
 930                 .gps_shdn = IMX_GPIO_NR(1, 27),
 931                 .vidin_en = IMX_GPIO_NR(3, 31),
 932                 .usb_sel = IMX_GPIO_NR(1, 2),
 933                 .wdis = IMX_GPIO_NR(7, 12),
 934         },
 935
 936         /* GW53xx */
 937         {
 938                 .gpio_pads = gw53xx_gpio_pads,
 939                 .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
 940                 .dio_cfg = {
 941                         {
 942                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 943                                 IMX_GPIO_NR(1, 16),
 944                                 { 0, 0 },
 945                                 0
 946                         },
 947                         {
 948                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 949                                 IMX_GPIO_NR(1, 19),
 950                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 951                                 2
 952                         },
 953                         {
 954                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 955                                 IMX_GPIO_NR(1, 17),
 956                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 957                                 3
 958                         },
 959                         {
 960                                 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
 961                                 IMX_GPIO_NR(1, 20),
 962                                 { 0, 0 },
 963                                 0
 964                         },
 965                 },
 966                 .num_gpios = 4,
 967                 .leds = {
 968                         IMX_GPIO_NR(4, 6),
 969                         IMX_GPIO_NR(4, 7),
 970                         IMX_GPIO_NR(4, 15),
 971                 },
 972                 .pcie_rst = IMX_GPIO_NR(1, 29),
 973                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 974                 .mezz_irq = IMX_GPIO_NR(2, 18),
 975                 .gps_shdn = IMX_GPIO_NR(1, 27),
 976                 .vidin_en = IMX_GPIO_NR(3, 31),
 977                 .wdis = IMX_GPIO_NR(7, 12),
 978         },
 979
 980         /* GW54xx */
 981         {
 982                 .gpio_pads = gw54xx_gpio_pads,
 983                 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
 984                 .dio_cfg = {
 985                         {
 986                                 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
 987                                 IMX_GPIO_NR(1, 9),
 988                                 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
 989                                 1
 990                         },
 991                         {
 992                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 993                                 IMX_GPIO_NR(1, 19),
 994                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 995                                 2
 996                         },
 997                         {
 998                                 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
 999                                 IMX_GPIO_NR(2, 9),
1000                                 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
1001                                 3
1002                         },
1003                         {
1004                                 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
1005                                 IMX_GPIO_NR(2, 10),
1006                                 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
1007                                 4
1008                         },
1009                 },
1010                 .num_gpios = 4,
1011                 .leds = {
1012                         IMX_GPIO_NR(4, 6),
1013                         IMX_GPIO_NR(4, 7),
1014                         IMX_GPIO_NR(4, 15),
1015                 },
1016                 .pcie_rst = IMX_GPIO_NR(1, 29),
1017                 .mezz_pwren = IMX_GPIO_NR(2, 19),
1018                 .mezz_irq = IMX_GPIO_NR(2, 18),
1019                 .rs485en = IMX_GPIO_NR(7, 1),
1020                 .vidin_en = IMX_GPIO_NR(3, 31),
1021                 .dioi2c_en = IMX_GPIO_NR(4,  5),
1022                 .pcie_sson = IMX_GPIO_NR(1, 20),
1023                 .wdis = IMX_GPIO_NR(5, 17),
1024         },
1025
1026         /* GW551x */
1027         {
1028                 .gpio_pads = gw551x_gpio_pads,
1029                 .num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2,
1030                 .dio_cfg = {
1031                         {
1032                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
1033                                 IMX_GPIO_NR(1, 16),
1034                                 { 0, 0 },
1035                                 0
1036                         },
1037                         {
1038                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
1039                                 IMX_GPIO_NR(1, 19),
1040                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
1041                                 2
1042                         },
1043                         {
1044                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
1045                                 IMX_GPIO_NR(1, 17),
1046                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
1047                                 3
1048                         },
1049                         {
1050                                 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
1051                                 IMX_GPIO_NR(1, 18),
1052                                 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
1053                                 4
1054                         },
1055                 },
1056                 .num_gpios = 2,
1057                 .leds = {
1058                         IMX_GPIO_NR(4, 7),
1059                 },
1060                 .pcie_rst = IMX_GPIO_NR(1, 0),
1061                 .wdis = IMX_GPIO_NR(7, 12),
1062         },
1063
1064         /* GW552x */
1065         {
1066                 .gpio_pads = gw552x_gpio_pads,
1067                 .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
1068                 .dio_cfg = {
1069                         {
1070                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
1071                                 IMX_GPIO_NR(1, 19),
1072                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
1073                                 2
1074                         },
1075                         {
1076                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
1077                                 IMX_GPIO_NR(1, 17),
1078                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
1079                                 3
1080                         },
1081                 },
1082                 .num_gpios = 4,
1083                 .leds = {
1084                         IMX_GPIO_NR(4, 6),
1085                         IMX_GPIO_NR(4, 7),
1086                         IMX_GPIO_NR(4, 15),
1087                 },
1088                 .pcie_rst = IMX_GPIO_NR(1, 29),
1089                 .wdis = IMX_GPIO_NR(7, 12),
1090         },
1091 };
1092
1093 /* setup board specific PMIC */
1094 int power_init_board(void)
1095 {
1096         struct pmic *p;
1097         u32 reg;
1098
1099         /* configure PFUZE100 PMIC */
1100         if (board_type == GW54xx || board_type == GW54proto) {
1101                 power_pfuze100_init(CONFIG_I2C_PMIC);
1102                 p = pmic_get("PFUZE100");
1103                 if (p && !pmic_probe(p)) {
1104                         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
1105                         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
1106
1107                         /* Set VGEN1 to 1.5V and enable */
1108                         pmic_reg_read(p, PFUZE100_VGEN1VOL, &reg);
1109                         reg &= ~(LDO_VOL_MASK);
1110                         reg |= (LDOA_1_50V | LDO_EN);
1111                         pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
1112
1113                         /* Set SWBST to 5.0V and enable */
1114                         pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
1115                         reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
1116                         reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
1117                         pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
1118                 }
1119         }
1120
1121         /* configure LTC3676 PMIC */
1122         else {
1123                 power_ltc3676_init(CONFIG_I2C_PMIC);
1124                 p = pmic_get("LTC3676_PMIC");
1125                 if (p && !pmic_probe(p)) {
1126                         puts("PMIC:  LTC3676\n");
1127                         /*
1128                          * set board-specific scalar for max CPU frequency
1129                          * per CPU based on the LDO enabled Operating Ranges
1130                          * defined in the respective IMX6DQ and IMX6SDL
1131                          * datasheets. The voltage resulting from the R1/R2
1132                          * feedback inputs on Ventana is 1308mV. Note that this
1133                          * is a bit shy of the Vmin of 1350mV in the datasheet
1134                          * for LDO enabled mode but is as high as we can go.
1135                          *
1136                          * We will rely on an OS kernel driver to properly
1137                          * regulate these per CPU operating point and use LDO
1138                          * bypass mode when using the higher frequency
1139                          * operating points to compensate as LDO bypass mode
1140                          * allows the rails be 125mV lower.
1141                          */
1142                         /* mask PGOOD during SW1 transition */
1143                         pmic_reg_write(p, LTC3676_DVB1B,
1144                                        0x1f | LTC3676_PGOOD_MASK);
1145                         /* set SW1 (VDD_SOC) */
1146                         pmic_reg_write(p, LTC3676_DVB1A, 0x1f);
1147
1148                         /* mask PGOOD during SW3 transition */
1149                         pmic_reg_write(p, LTC3676_DVB3B,
1150                                        0x1f | LTC3676_PGOOD_MASK);
1151                         /* set SW3 (VDD_ARM) */
1152                         pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
1153                 }
1154         }
1155
1156         return 0;
1157 }
1158
1159 /* setup GPIO pinmux and default configuration per baseboard */
1160 static void setup_board_gpio(int board)
1161 {
1162         struct ventana_board_info *info = &ventana_info;
1163         const char *s;
1164         char arg[10];
1165         size_t len;
1166         int i;
1167         int quiet = simple_strtol(getenv("quiet"), NULL, 10);
1168
1169         if (board >= GW_UNKNOWN)
1170                 return;
1171
1172         /* RS232_EN# */
1173         gpio_request(GP_RS232_EN, "rs232_en");
1174         gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
1175
1176         /* MSATA Enable */
1177         gpio_request(GP_MSATA_SEL, "msata_en");
1178         if (is_cpu_type(MXC_CPU_MX6Q) &&
1179             test_bit(EECONFIG_SATA, info->config)) {
1180                 gpio_direction_output(GP_MSATA_SEL,
1181                                       (hwconfig("msata")) ?  1 : 0);
1182         } else {
1183                 gpio_direction_output(GP_MSATA_SEL, 0);
1184         }
1185
1186 #if !defined(CONFIG_CMD_PCI)
1187         /* GW522x Uses GPIO3_IO23 for PCIE_RST# */
1188         if (board_type == GW52xx && info->model[4] == '2')
1189                 gpio_cfg[board].pcie_rst = IMX_GPIO_NR(3, 23);
1190
1191         /* assert PCI_RST# (released by OS when clock is valid) */
1192         gpio_request(gpio_cfg[board].pcie_rst, "pci_rst#");
1193         gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
1194 #endif
1195
1196         /* turn off (active-high) user LED's */
1197         for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) {
1198                 if (gpio_cfg[board].leds[i]) {
1199                         gpio_requestf(gpio_cfg[board].leds[i], "led_user%d", i);
1200                         gpio_direction_output(gpio_cfg[board].leds[i], 1);
1201                 }
1202         }
1203
1204         /* Expansion Mezzanine IO */
1205         if (gpio_cfg[board].mezz_pwren) {
1206                 gpio_request(gpio_cfg[board].mezz_pwren, "mezz_pwr");
1207                 gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
1208         }
1209         if (gpio_cfg[board].mezz_irq) {
1210                 gpio_request(gpio_cfg[board].mezz_irq, "mezz_irq#");
1211                 gpio_direction_input(gpio_cfg[board].mezz_irq);
1212         }
1213
1214         /* RS485 Transmit Enable */
1215         if (gpio_cfg[board].rs485en) {
1216                 gpio_request(gpio_cfg[board].rs485en, "rs485_en");
1217                 gpio_direction_output(gpio_cfg[board].rs485en, 0);
1218         }
1219
1220         /* GPS_SHDN */
1221         if (gpio_cfg[board].gps_shdn) {
1222                 gpio_request(gpio_cfg[board].gps_shdn, "gps_shdn");
1223                 gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
1224         }
1225
1226         /* Analog video codec power enable */
1227         if (gpio_cfg[board].vidin_en) {
1228                 gpio_request(gpio_cfg[board].vidin_en, "anavidin_en");
1229                 gpio_direction_output(gpio_cfg[board].vidin_en, 1);
1230         }
1231
1232         /* DIOI2C_DIS# */
1233         if (gpio_cfg[board].dioi2c_en) {
1234                 gpio_request(gpio_cfg[board].dioi2c_en, "dioi2c_dis#");
1235                 gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
1236         }
1237
1238         /* PCICK_SSON: disable spread-spectrum clock */
1239         if (gpio_cfg[board].pcie_sson) {
1240                 gpio_request(gpio_cfg[board].pcie_sson, "pci_sson");
1241                 gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
1242         }
1243
1244         /* USBOTG Select (PCISKT or FrontPanel) */
1245         if (gpio_cfg[board].usb_sel) {
1246                 gpio_request(gpio_cfg[board].usb_sel, "usb_pcisel");
1247                 gpio_direction_output(gpio_cfg[board].usb_sel,
1248                                       (hwconfig("usb_pcisel")) ? 1 : 0);
1249         }
1250
1251
1252         /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
1253         if (gpio_cfg[board].wdis) {
1254                 gpio_request(gpio_cfg[board].wdis, "wlan_dis");
1255                 gpio_direction_output(gpio_cfg[board].wdis, 1);
1256         }
1257
1258         /*
1259          * Configure DIO pinmux/padctl registers
1260          * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
1261          */
1262         for (i = 0; i < 4; i++) {
1263                 struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
1264                 iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
1265                 unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
1266
1267                 if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1])
1268                         continue;
1269                 sprintf(arg, "dio%d", i);
1270                 if (!hwconfig(arg))
1271                         continue;
1272                 s = hwconfig_subarg(arg, "padctrl", &len);
1273                 if (s) {
1274                         ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16)
1275                                             & 0x1ffff) | MUX_MODE_SION;
1276                 }
1277                 if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
1278                         if (!quiet) {
1279                                 printf("DIO%d:  GPIO%d_IO%02d (gpio-%d)\n", i,
1280                                        (cfg->gpio_param/32)+1,
1281                                        cfg->gpio_param%32,
1282                                        cfg->gpio_param);
1283                         }
1284                         imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
1285                                                ctrl);
1286                         gpio_requestf(cfg->gpio_param, "dio%d", i);
1287                         gpio_direction_input(cfg->gpio_param);
1288                 } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
1289                            cfg->pwm_padmux) {
1290                         if (!quiet)
1291                                 printf("DIO%d:  pwm%d\n", i, cfg->pwm_param);
1292                         imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
1293                                                MUX_PAD_CTRL(ctrl));
1294                 }
1295         }
1296
1297         if (!quiet) {
1298                 if (is_cpu_type(MXC_CPU_MX6Q) &&
1299                     (test_bit(EECONFIG_SATA, info->config))) {
1300                         printf("MSATA: %s\n", (hwconfig("msata") ?
1301                                "enabled" : "disabled"));
1302                 }
1303                 printf("RS232: %s\n", (hwconfig("rs232")) ?
1304                        "enabled" : "disabled");
1305         }
1306 }
1307
1308 #if defined(CONFIG_CMD_PCI)
1309 int imx6_pcie_toggle_reset(void)
1310 {
1311         if (board_type < GW_UNKNOWN) {
1312                 uint pin = gpio_cfg[board_type].pcie_rst;
1313                 gpio_request(pin, "pci_rst#");
1314                 gpio_direction_output(pin, 0);
1315                 mdelay(50);
1316                 gpio_direction_output(pin, 1);
1317         }
1318         return 0;
1319 }
1320
1321 /*
1322  * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
1323  * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
1324  * properly and assert reset for 100ms.
1325  */
1326 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
1327                          unsigned short vendor, unsigned short device,
1328                          unsigned short class)
1329 {
1330         u32 dw;
1331
1332         debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
1333               PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
1334         if (vendor == PCI_VENDOR_ID_PLX &&
1335             (device & 0xfff0) == 0x8600 &&
1336             PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
1337                 debug("configuring PLX 860X downstream PERST#\n");
1338                 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
1339                 dw |= 0xaaa8; /* GPIO1-7 outputs */
1340                 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
1341
1342                 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
1343                 dw |= 0xfe;   /* GPIO1-7 output high */
1344                 pci_hose_write_config_dword(hose, dev, 0x644, dw);
1345
1346                 mdelay(100);
1347         }
1348 }
1349 #endif /* CONFIG_CMD_PCI */
1350
1351 #ifdef CONFIG_SERIAL_TAG
1352 /*
1353  * called when setting up ATAGS before booting kernel
1354  * populate serialnum from the following (in order of priority):
1355  *   serial# env var
1356  *   eeprom
1357  */
1358 void get_board_serial(struct tag_serialnr *serialnr)
1359 {
1360         char *serial = getenv("serial#");
1361
1362         if (serial) {
1363                 serialnr->high = 0;
1364                 serialnr->low = simple_strtoul(serial, NULL, 10);
1365         } else if (ventana_info.model[0]) {
1366                 serialnr->high = 0;
1367                 serialnr->low = ventana_info.serial;
1368         } else {
1369                 serialnr->high = 0;
1370                 serialnr->low = 0;
1371         }
1372 }
1373 #endif
1374
1375 /*
1376  * Board Support
1377  */
1378
1379 /* called from SPL board_init_f() */
1380 int board_early_init_f(void)
1381 {
1382         setup_iomux_uart();
1383
1384         gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
1385
1386 #if defined(CONFIG_VIDEO_IPUV3)
1387         setup_display();
1388 #endif
1389         return 0;
1390 }
1391
1392 int dram_init(void)
1393 {
1394         gd->ram_size = imx_ddr_size();
1395         return 0;
1396 }
1397
1398 int board_init(void)
1399 {
1400         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
1401
1402         clrsetbits_le32(&iomuxc_regs->gpr[1],
1403                         IOMUXC_GPR1_OTG_ID_MASK,
1404                         IOMUXC_GPR1_OTG_ID_GPIO1);
1405
1406         /* address of linux boot parameters */
1407         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
1408
1409 #ifdef CONFIG_CMD_NAND
1410         setup_gpmi_nand();
1411 #endif
1412 #ifdef CONFIG_MXC_SPI
1413         setup_spi();
1414 #endif
1415         if (is_cpu_type(MXC_CPU_MX6Q)) {
1416                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
1417                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
1418                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
1419         } else {
1420                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
1421                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
1422                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
1423         }
1424
1425 #ifdef CONFIG_CMD_SATA
1426         setup_sata();
1427 #endif
1428         /* read Gateworks EEPROM into global struct (used later) */
1429         board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
1430
1431         /* board-specifc GPIO iomux */
1432         SETUP_IOMUX_PADS(gw_gpio_pads);
1433         if (board_type < GW_UNKNOWN) {
1434                 iomux_v3_cfg_t const *p = gpio_cfg[board_type].gpio_pads;
1435                 int count = gpio_cfg[board_type].num_pads;
1436
1437                 imx_iomux_v3_setup_multiple_pads(p, count);
1438         }
1439
1440         return 0;
1441 }
1442
1443 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
1444 /*
1445  * called during late init (after relocation and after board_init())
1446  * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
1447  * EEPROM read.
1448  */
1449 int checkboard(void)
1450 {
1451         struct ventana_board_info *info = &ventana_info;
1452         unsigned char buf[4];
1453         const char *p;
1454         int quiet; /* Quiet or minimal output mode */
1455
1456         quiet = 0;
1457         p = getenv("quiet");
1458         if (p)
1459                 quiet = simple_strtol(p, NULL, 10);
1460         else
1461                 setenv("quiet", "0");
1462
1463         puts("\nGateworks Corporation Copyright 2014\n");
1464         if (info->model[0]) {
1465                 printf("Model: %s\n", info->model);
1466                 printf("MFGDate: %02x-%02x-%02x%02x\n",
1467                        info->mfgdate[0], info->mfgdate[1],
1468                        info->mfgdate[2], info->mfgdate[3]);
1469                 printf("Serial:%d\n", info->serial);
1470         } else {
1471                 puts("Invalid EEPROM - board will not function fully\n");
1472         }
1473         if (quiet)
1474                 return 0;
1475
1476         /* Display GSC firmware revision/CRC/status */
1477         gsc_info(0);
1478
1479         /* Display RTC */
1480         if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
1481                 printf("RTC:   %d\n",
1482                        buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
1483         }
1484
1485         return 0;
1486 }
1487 #endif
1488
1489 #ifdef CONFIG_CMD_BMODE
1490 /*
1491  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
1492  * see Table 8-11 and Table 5-9
1493  *  BOOT_CFG1[7] = 1 (boot from NAND)
1494  *  BOOT_CFG1[5] = 0 - raw NAND
1495  *  BOOT_CFG1[4] = 0 - default pad settings
1496  *  BOOT_CFG1[3:2] = 00 - devices = 1
1497  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
1498  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
1499  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
1500  *  BOOT_CFG2[0] = 0 - Reset time 12ms
1501  */
1502 static const struct boot_mode board_boot_modes[] = {
1503         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
1504         { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
1505         { NULL, 0 },
1506 };
1507 #endif
1508
1509 /* late init */
1510 int misc_init_r(void)
1511 {
1512         struct ventana_board_info *info = &ventana_info;
1513         unsigned char reg;
1514
1515         /* set env vars based on EEPROM data */
1516         if (ventana_info.model[0]) {
1517                 char str[16], fdt[36];
1518                 char *p;
1519                 const char *cputype = "";
1520                 int i;
1521
1522                 /*
1523                  * FDT name will be prefixed with CPU type.  Three versions
1524                  * will be created each increasingly generic and bootloader
1525                  * env scripts will try loading each from most specific to
1526                  * least.
1527                  */
1528                 if (is_cpu_type(MXC_CPU_MX6Q) ||
1529                     is_cpu_type(MXC_CPU_MX6D))
1530                         cputype = "imx6q";
1531                 else if (is_cpu_type(MXC_CPU_MX6DL) ||
1532                          is_cpu_type(MXC_CPU_MX6SOLO))
1533                         cputype = "imx6dl";
1534                 setenv("soctype", cputype);
1535                 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
1536                         setenv("flash_layout", "large");
1537                 else
1538                         setenv("flash_layout", "normal");
1539                 memset(str, 0, sizeof(str));
1540                 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
1541                         str[i] = tolower(info->model[i]);
1542                 if (!getenv("model"))
1543                         setenv("model", str);
1544                 if (!getenv("fdt_file")) {
1545                         sprintf(fdt, "%s-%s.dtb", cputype, str);
1546                         setenv("fdt_file", fdt);
1547                 }
1548                 p = strchr(str, '-');
1549                 if (p) {
1550                         *p++ = 0;
1551
1552                         setenv("model_base", str);
1553                         if (!getenv("fdt_file1")) {
1554                                 sprintf(fdt, "%s-%s.dtb", cputype, str);
1555                                 setenv("fdt_file1", fdt);
1556                         }
1557                         if (board_type != GW551x && board_type != GW552x)
1558                                 str[4] = 'x';
1559                         str[5] = 'x';
1560                         str[6] = 0;
1561                         if (!getenv("fdt_file2")) {
1562                                 sprintf(fdt, "%s-%s.dtb", cputype, str);
1563                                 setenv("fdt_file2", fdt);
1564                         }
1565                 }
1566
1567                 /* initialize env from EEPROM */
1568                 if (test_bit(EECONFIG_ETH0, info->config) &&
1569                     !getenv("ethaddr")) {
1570                         eth_setenv_enetaddr("ethaddr", info->mac0);
1571                 }
1572                 if (test_bit(EECONFIG_ETH1, info->config) &&
1573                     !getenv("eth1addr")) {
1574                         eth_setenv_enetaddr("eth1addr", info->mac1);
1575                 }
1576
1577                 /* board serial-number */
1578                 sprintf(str, "%6d", info->serial);
1579                 setenv("serial#", str);
1580
1581                 /* memory MB */
1582                 sprintf(str, "%d", (int) (gd->ram_size >> 20));
1583                 setenv("mem_mb", str);
1584         }
1585
1586
1587         /* setup baseboard specific GPIO pinmux and config */
1588         setup_board_gpio(board_type);
1589
1590 #ifdef CONFIG_CMD_BMODE
1591         add_board_boot_modes(board_boot_modes);
1592 #endif
1593
1594         /*
1595          *  The Gateworks System Controller implements a boot
1596          *  watchdog (always enabled) as a workaround for IMX6 boot related
1597          *  errata such as:
1598          *    ERR005768 - no fix scheduled
1599          *    ERR006282 - fixed in silicon r1.2
1600          *    ERR007117 - fixed in silicon r1.3
1601          *    ERR007220 - fixed in silicon r1.3
1602          *    ERR007926 - no fix scheduled
1603          *  see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
1604          *
1605          * Disable the boot watchdog and display/clear the timeout flag if set
1606          */
1607         i2c_set_bus_num(CONFIG_I2C_GSC);
1608         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) {
1609                 reg |= (1 << GSC_SC_CTRL1_WDDIS);
1610                 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
1611                         puts("Error: could not disable GSC Watchdog\n");
1612         } else {
1613                 puts("Error: could not disable GSC Watchdog\n");
1614         }
1615
1616         return 0;
1617 }
1618
1619 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1620
1621 static int ft_sethdmiinfmt(void *blob, char *mode)
1622 {
1623         int off;
1624
1625         if (!mode)
1626                 return -EINVAL;
1627
1628         off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
1629         if (off < 0)
1630                 return off;
1631
1632         if (0 == strcasecmp(mode, "yuv422bt656")) {
1633                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
1634                              0x00, 0x00, 0x00 };
1635                 mode = "422_ccir";
1636                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
1637                 fdt_setprop_u32(blob, off, "vidout_trc", 1);
1638                 fdt_setprop_u32(blob, off, "vidout_blc", 1);
1639                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
1640                 printf("   set HDMI input mode to %s\n", mode);
1641         } else if (0 == strcasecmp(mode, "yuv422smp")) {
1642                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
1643                              0x82, 0x81, 0x00 };
1644                 mode = "422_smp";
1645                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
1646                 fdt_setprop_u32(blob, off, "vidout_trc", 0);
1647                 fdt_setprop_u32(blob, off, "vidout_blc", 0);
1648                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
1649                 printf("   set HDMI input mode to %s\n", mode);
1650         } else {
1651                 return -EINVAL;
1652         }
1653
1654         return 0;
1655 }
1656
1657 /*
1658  * called prior to booting kernel or by 'fdt boardsetup' command
1659  *
1660  * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1661  *  - mtd partitions based on mtdparts/mtdids env
1662  *  - system-serial (board serial num from EEPROM)
1663  *  - board (full model from EEPROM)
1664  *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
1665  */
1666 int ft_board_setup(void *blob, bd_t *bd)
1667 {
1668         struct ventana_board_info *info = &ventana_info;
1669         struct ventana_eeprom_config *cfg;
1670         struct node_info nodes[] = {
1671                 { "sst,w25q256",          MTD_DEV_TYPE_NOR, },  /* SPI flash */
1672                 { "fsl,imx6q-gpmi-nand",  MTD_DEV_TYPE_NAND, }, /* NAND flash */
1673         };
1674         const char *model = getenv("model");
1675         const char *display = getenv("display");
1676         int i;
1677         char rev = 0;
1678
1679         /* determine board revision */
1680         for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1681                 if (ventana_info.model[i] >= 'A') {
1682                         rev = ventana_info.model[i];
1683                         break;
1684                 }
1685         }
1686
1687         if (getenv("fdt_noauto")) {
1688                 puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
1689                 return 0;
1690         }
1691
1692         /* Update partition nodes using info from mtdparts env var */
1693         puts("   Updating MTD partitions...\n");
1694         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1695
1696         /* Update display timings from display env var */
1697         if (display) {
1698                 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
1699                                       display) >= 0)
1700                         printf("   Set display timings for %s...\n", display);
1701         }
1702
1703         if (!model) {
1704                 puts("invalid board info: Leaving FDT fully enabled\n");
1705                 return 0;
1706         }
1707         printf("   Adjusting FDT per EEPROM for %s...\n", model);
1708
1709         /* board serial number */
1710         fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
1711                     strlen(getenv("serial#")) + 1);
1712
1713         /* board (model contains model from device-tree) */
1714         fdt_setprop(blob, 0, "board", info->model,
1715                     strlen((const char *)info->model) + 1);
1716
1717         /* set desired digital video capture format */
1718         ft_sethdmiinfmt(blob, getenv("hdmiinfmt"));
1719
1720         /*
1721          * disable serial2 node for GW54xx for compatibility with older
1722          * 3.10.x kernel that improperly had this node enabled in the DT
1723          */
1724         if (board_type == GW54xx) {
1725                 i = fdt_path_offset(blob,
1726                                     "/soc/aips-bus@02100000/serial@021ec000");
1727                 if (i)
1728                         fdt_del_node(blob, i);
1729         }
1730
1731         /*
1732          * disable wdog1/wdog2 nodes for GW51xx below revC to work around
1733          * errata causing wdog timer to be unreliable.
1734          */
1735         if (board_type == GW51xx && rev >= 'A' && rev < 'C') {
1736                 i = fdt_path_offset(blob,
1737                                     "/soc/aips-bus@02000000/wdog@020bc000");
1738                 if (i)
1739                         fdt_status_disabled(blob, i);
1740         }
1741
1742         /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
1743         else if (board_type == GW52xx && info->model[4] == '2') {
1744                 u32 handle = 0;
1745                 u32 *range = NULL;
1746
1747                 i = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
1748                 if (i)
1749                         range = (u32 *)fdt_getprop(blob, i, "reset-gpio",
1750                                                    NULL);
1751
1752                 if (range) {
1753                         i = fdt_path_offset(blob,
1754                                             "/soc/aips-bus@02000000/gpio@020a4000");
1755                         if (i)
1756                                 handle = fdt_get_phandle(blob, i);
1757                         if (handle) {
1758                                 range[0] = cpu_to_fdt32(handle);
1759                                 range[1] = cpu_to_fdt32(23);
1760                         }
1761                 }
1762         }
1763
1764         /*
1765          * isolate CSI0_DATA_EN for GW551x below revB to work around
1766          * errata causing non functional digital video in (it is not hooked up)
1767          */
1768         else if (board_type == GW551x && rev == 'A') {
1769                 u32 *range = NULL;
1770                 int len;
1771                 const u32 *handle = NULL;
1772
1773                 i = fdt_node_offset_by_compatible(blob, -1,
1774                                                   "fsl,imx-tda1997x-video");
1775                 if (i)
1776                         handle = fdt_getprop(blob, i, "pinctrl-0", NULL);
1777                 if (handle)
1778                         i = fdt_node_offset_by_phandle(blob,
1779                                                        fdt32_to_cpu(*handle));
1780                 if (i)
1781                         range = (u32 *)fdt_getprop(blob, i, "fsl,pins", &len);
1782                 if (range) {
1783                         len /= sizeof(u32);
1784                         for (i = 0; i < len; i += 6) {
1785                                 u32 mux_reg = fdt32_to_cpu(range[i+0]);
1786                                 u32 conf_reg = fdt32_to_cpu(range[i+1]);
1787                                 /* mux PAD_CSI0_DATA_EN to GPIO */
1788                                 if (is_cpu_type(MXC_CPU_MX6Q) &&
1789                                     mux_reg == 0x260 && conf_reg == 0x630)
1790                                         range[i+3] = cpu_to_fdt32(0x5);
1791                                 else if (!is_cpu_type(MXC_CPU_MX6Q) &&
1792                                     mux_reg == 0x08c && conf_reg == 0x3a0)
1793                                         range[i+3] = cpu_to_fdt32(0x5);
1794                         }
1795                         fdt_setprop_inplace(blob, i, "fsl,pins", range, len);
1796                 }
1797
1798                 /* set BT656 video format */
1799                 ft_sethdmiinfmt(blob, "yuv422bt656");
1800         }
1801
1802         /*
1803          * Peripheral Config:
1804          *  remove nodes by alias path if EEPROM config tells us the
1805          *  peripheral is not loaded on the board.
1806          */
1807         if (getenv("fdt_noconfig")) {
1808                 puts("   Skiping periperhal config (fdt_noconfig defined)\n");
1809                 return 0;
1810         }
1811         cfg = econfig;
1812         while (cfg->name) {
1813                 if (!test_bit(cfg->bit, info->config)) {
1814                         fdt_del_node_and_alias(blob, cfg->dtalias ?
1815                                                cfg->dtalias : cfg->name);
1816                 }
1817                 cfg++;
1818         }
1819
1820         return 0;
1821 }
1822 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
1823
1824 static struct mxc_serial_platdata ventana_mxc_serial_plat = {
1825         .reg = (struct mxc_uart *)UART2_BASE,
1826 };
1827
1828 U_BOOT_DEVICE(ventana_serial) = {
1829         .name   = "serial_mxc",
1830         .platdata = &ventana_mxc_serial_plat,
1831 };