board/gateworks/gw_ventana/gw_ventana.c

   1 /*
   2  * Copyright (C) 2013 Gateworks Corporation
   3  *
   4  * Author: Tim Harvey <tharvey@gateworks.com>
   5  *
   6  * SPDX-License-Identifier: GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/mxc_hdmi.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/gpio.h>
  19 #include <asm/imx-common/iomux-v3.h>
  20 #include <asm/imx-common/mxc_i2c.h>
  21 #include <asm/imx-common/boot_mode.h>
  22 #include <asm/imx-common/sata.h>
  23 #include <asm/imx-common/video.h>
  24 #include <jffs2/load_kernel.h>
  25 #include <hwconfig.h>
  26 #include <i2c.h>
  27 #include <linux/ctype.h>
  28 #include <fdt_support.h>
  29 #include <fsl_esdhc.h>
  30 #include <miiphy.h>
  31 #include <mmc.h>
  32 #include <mtd_node.h>
  33 #include <netdev.h>
  34 #include <power/pmic.h>
  35 #include <power/ltc3676_pmic.h>
  36 #include <power/pfuze100_pmic.h>
  37 #include <fdt_support.h>
  38 #include <jffs2/load_kernel.h>
  39 #include <spi_flash.h>
  40
  41 #include "gsc.h"
  42 #include "ventana_eeprom.h"
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 /* GPIO's common to all baseboards */
  47 #define GP_PHY_RST      IMX_GPIO_NR(1, 30)
  48 #define GP_USB_OTG_PWR  IMX_GPIO_NR(3, 22)
  49 #define GP_SD3_CD       IMX_GPIO_NR(7, 0)
  50 #define GP_RS232_EN     IMX_GPIO_NR(2, 11)
  51 #define GP_MSATA_SEL    IMX_GPIO_NR(2, 8)
  52
  53 /* I2C bus numbers */
  54 #define I2C_GSC         0
  55 #define I2C_PMIC        1
  56
  57 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  58         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  59         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  60
  61 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  62         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
  63         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  64
  65 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  66         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  67         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  68
  69 #define SPI_PAD_CTRL (PAD_CTL_HYS |                             \
  70         PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
  71         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  72
  73 #define DIO_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |              \
  74         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  75         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  76
  77 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  78         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  79         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  80
  81 #define IRQ_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |              \
  82         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  83         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  84
  85 #define DIO_PAD_CFG   (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION)
  86
  87
  88 /*
  89  * EEPROM board info struct populated by read_eeprom so that we only have to
  90  * read it once.
  91  */
  92 static struct ventana_board_info ventana_info;
  93
  94 int board_type;
  95
  96 /* UART1: Function varies per baseboard */
  97 iomux_v3_cfg_t const uart1_pads[] = {
  98         IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  99         IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 100 };
 101
 102 /* UART2: Serial Console */
 103 iomux_v3_cfg_t const uart2_pads[] = {
 104         IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 105         IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 106 };
 107
 108 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 109
 110 /* I2C1: GSC */
 111 struct i2c_pads_info mx6q_i2c_pad_info0 = {
 112         .scl = {
 113                 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
 114                 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
 115                 .gp = IMX_GPIO_NR(3, 21)
 116         },
 117         .sda = {
 118                 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
 119                 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
 120                 .gp = IMX_GPIO_NR(3, 28)
 121         }
 122 };
 123 struct i2c_pads_info mx6dl_i2c_pad_info0 = {
 124         .scl = {
 125                 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
 126                 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
 127                 .gp = IMX_GPIO_NR(3, 21)
 128         },
 129         .sda = {
 130                 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
 131                 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
 132                 .gp = IMX_GPIO_NR(3, 28)
 133         }
 134 };
 135
 136 /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
 137 struct i2c_pads_info mx6q_i2c_pad_info1 = {
 138         .scl = {
 139                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
 140                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
 141                 .gp = IMX_GPIO_NR(4, 12)
 142         },
 143         .sda = {
 144                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
 145                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 146                 .gp = IMX_GPIO_NR(4, 13)
 147         }
 148 };
 149 struct i2c_pads_info mx6dl_i2c_pad_info1 = {
 150         .scl = {
 151                 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
 152                 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
 153                 .gp = IMX_GPIO_NR(4, 12)
 154         },
 155         .sda = {
 156                 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
 157                 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 158                 .gp = IMX_GPIO_NR(4, 13)
 159         }
 160 };
 161
 162 /* I2C3: Misc/Expansion */
 163 struct i2c_pads_info mx6q_i2c_pad_info2 = {
 164         .scl = {
 165                 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
 166                 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
 167                 .gp = IMX_GPIO_NR(1, 3)
 168         },
 169         .sda = {
 170                 .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
 171                 .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
 172                 .gp = IMX_GPIO_NR(1, 6)
 173         }
 174 };
 175 struct i2c_pads_info mx6dl_i2c_pad_info2 = {
 176         .scl = {
 177                 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
 178                 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
 179                 .gp = IMX_GPIO_NR(1, 3)
 180         },
 181         .sda = {
 182                 .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
 183                 .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
 184                 .gp = IMX_GPIO_NR(1, 6)
 185         }
 186 };
 187
 188 /* MMC */
 189 iomux_v3_cfg_t const usdhc3_pads[] = {
 190         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 191         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 192         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 193         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 194         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 195         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 196         /* CD */
 197         IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00  | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 198 };
 199
 200 /* ENET */
 201 iomux_v3_cfg_t const enet_pads[] = {
 202         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 203         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 204         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 205         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 206         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 207         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 208         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 209         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
 210                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 211         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
 212                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 213         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 214         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 215         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 216         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 217         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 218         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
 219                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 220         /* PHY nRST */
 221         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
 222 };
 223
 224 /* NAND */
 225 iomux_v3_cfg_t const nfc_pads[] = {
 226         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 227         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 228         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 229         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 230         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 231         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 232         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 233         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 234         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 235         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 236         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 237         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 238         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 239         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 240         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 241 };
 242
 243 #ifdef CONFIG_CMD_NAND
 244 static void setup_gpmi_nand(void)
 245 {
 246         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 247
 248         /* config gpmi nand iomux */
 249         SETUP_IOMUX_PADS(nfc_pads);
 250
 251         /* config gpmi and bch clock to 100 MHz */
 252         clrsetbits_le32(&mxc_ccm->cs2cdr,
 253                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 254                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 255                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 256                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 257                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 258                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 259
 260         /* enable gpmi and bch clock gating */
 261         setbits_le32(&mxc_ccm->CCGR4,
 262                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 263                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 264                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 265                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 266                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 267
 268         /* enable apbh clock gating */
 269         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 270 }
 271 #endif
 272
 273 static void setup_iomux_enet(void)
 274 {
 275         SETUP_IOMUX_PADS(enet_pads);
 276
 277         /* toggle PHY_RST# */
 278         gpio_direction_output(GP_PHY_RST, 0);
 279         mdelay(2);
 280         gpio_set_value(GP_PHY_RST, 1);
 281 }
 282
 283 static void setup_iomux_uart(void)
 284 {
 285         SETUP_IOMUX_PADS(uart1_pads);
 286         SETUP_IOMUX_PADS(uart2_pads);
 287 }
 288
 289 #ifdef CONFIG_USB_EHCI_MX6
 290 iomux_v3_cfg_t const usb_pads[] = {
 291         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID   | DIO_PAD_CFG),
 292         IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
 293         /* OTG PWR */
 294         IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22  | DIO_PAD_CFG),
 295 };
 296
 297 int board_ehci_hcd_init(int port)
 298 {
 299         struct ventana_board_info *info = &ventana_info;
 300
 301         SETUP_IOMUX_PADS(usb_pads);
 302
 303         /* Reset USB HUB (present on GW54xx/GW53xx) */
 304         switch (info->model[3]) {
 305         case '3': /* GW53xx */
 306                 SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG);
 307                 gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
 308                 mdelay(2);
 309                 gpio_set_value(IMX_GPIO_NR(1, 9), 1);
 310                 break;
 311         case '4': /* GW54xx */
 312                 SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG);
 313                 gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
 314                 mdelay(2);
 315                 gpio_set_value(IMX_GPIO_NR(1, 16), 1);
 316                 break;
 317         }
 318
 319         return 0;
 320 }
 321
 322 int board_ehci_power(int port, int on)
 323 {
 324         if (port)
 325                 return 0;
 326         gpio_set_value(GP_USB_OTG_PWR, on);
 327         return 0;
 328 }
 329 #endif /* CONFIG_USB_EHCI_MX6 */
 330
 331 #ifdef CONFIG_FSL_ESDHC
 332 struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
 333
 334 int board_mmc_getcd(struct mmc *mmc)
 335 {
 336         /* Card Detect */
 337         gpio_direction_input(GP_SD3_CD);
 338         return !gpio_get_value(GP_SD3_CD);
 339 }
 340
 341 int board_mmc_init(bd_t *bis)
 342 {
 343         /* Only one USDHC controller on Ventana */
 344         SETUP_IOMUX_PADS(usdhc3_pads);
 345         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 346         usdhc_cfg.max_bus_width = 4;
 347
 348         return fsl_esdhc_initialize(bis, &usdhc_cfg);
 349 }
 350 #endif /* CONFIG_FSL_ESDHC */
 351
 352 #ifdef CONFIG_MXC_SPI
 353 iomux_v3_cfg_t const ecspi1_pads[] = {
 354         /* SS1 */
 355         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 356         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 357         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 358         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 359 };
 360
 361 static void setup_spi(void)
 362 {
 363         gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
 364         SETUP_IOMUX_PADS(ecspi1_pads);
 365 }
 366 #endif
 367
 368 /* configure eth0 PHY board-specific LED behavior */
 369 int board_phy_config(struct phy_device *phydev)
 370 {
 371         unsigned short val;
 372
 373         /* Marvel 88E1510 */
 374         if (phydev->phy_id == 0x1410dd1) {
 375                 /*
 376                  * Page 3, Register 16: LED[2:0] Function Control Register
 377                  * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
 378                  * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
 379                  */
 380                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
 381                 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
 382                 val &= 0xff00;
 383                 val |= 0x0017;
 384                 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
 385                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 386         }
 387
 388         if (phydev->drv->config)
 389                 phydev->drv->config(phydev);
 390
 391         return 0;
 392 }
 393
 394 int board_eth_init(bd_t *bis)
 395 {
 396         setup_iomux_enet();
 397
 398 #ifdef CONFIG_FEC_MXC
 399         cpu_eth_init(bis);
 400 #endif
 401
 402 #ifdef CONFIG_CI_UDC
 403         /* For otg ethernet*/
 404         usb_eth_initialize(bis);
 405 #endif
 406
 407         return 0;
 408 }
 409
 410 #if defined(CONFIG_VIDEO_IPUV3)
 411
 412 static void enable_hdmi(struct display_info_t const *dev)
 413 {
 414         imx_enable_hdmi_phy();
 415 }
 416
 417 static int detect_i2c(struct display_info_t const *dev)
 418 {
 419         return i2c_set_bus_num(dev->bus) == 0 &&
 420                 i2c_probe(dev->addr) == 0;
 421 }
 422
 423 static void enable_lvds(struct display_info_t const *dev)
 424 {
 425         struct iomuxc *iomux = (struct iomuxc *)
 426                                 IOMUXC_BASE_ADDR;
 427
 428         /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
 429         u32 reg = readl(&iomux->gpr[2]);
 430         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 431         writel(reg, &iomux->gpr[2]);
 432
 433         /* Enable Backlight */
 434         SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
 435         gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
 436 }
 437
 438 struct display_info_t const displays[] = {{
 439         /* HDMI Output */
 440         .bus    = -1,
 441         .addr   = 0,
 442         .pixfmt = IPU_PIX_FMT_RGB24,
 443         .detect = detect_hdmi,
 444         .enable = enable_hdmi,
 445         .mode   = {
 446                 .name           = "HDMI",
 447                 .refresh        = 60,
 448                 .xres           = 1024,
 449                 .yres           = 768,
 450                 .pixclock       = 15385,
 451                 .left_margin    = 220,
 452                 .right_margin   = 40,
 453                 .upper_margin   = 21,
 454                 .lower_margin   = 7,
 455                 .hsync_len      = 60,
 456                 .vsync_len      = 10,
 457                 .sync           = FB_SYNC_EXT,
 458                 .vmode          = FB_VMODE_NONINTERLACED
 459 } }, {
 460         /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
 461         .bus    = 2,
 462         .addr   = 0x4,
 463         .pixfmt = IPU_PIX_FMT_LVDS666,
 464         .detect = detect_i2c,
 465         .enable = enable_lvds,
 466         .mode   = {
 467                 .name           = "Hannstar-XGA",
 468                 .refresh        = 60,
 469                 .xres           = 1024,
 470                 .yres           = 768,
 471                 .pixclock       = 15385,
 472                 .left_margin    = 220,
 473                 .right_margin   = 40,
 474                 .upper_margin   = 21,
 475                 .lower_margin   = 7,
 476                 .hsync_len      = 60,
 477                 .vsync_len      = 10,
 478                 .sync           = FB_SYNC_EXT,
 479                 .vmode          = FB_VMODE_NONINTERLACED
 480 } } };
 481 size_t display_count = ARRAY_SIZE(displays);
 482
 483 static void setup_display(void)
 484 {
 485         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 486         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 487         int reg;
 488
 489         enable_ipu_clock();
 490         imx_setup_hdmi();
 491         /* Turn on LDB0,IPU,IPU DI0 clocks */
 492         reg = __raw_readl(&mxc_ccm->CCGR3);
 493         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 494         writel(reg, &mxc_ccm->CCGR3);
 495
 496         /* set LDB0, LDB1 clk select to 011/011 */
 497         reg = readl(&mxc_ccm->cs2cdr);
 498         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 499                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 500         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 501               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 502         writel(reg, &mxc_ccm->cs2cdr);
 503
 504         reg = readl(&mxc_ccm->cscmr2);
 505         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 506         writel(reg, &mxc_ccm->cscmr2);
 507
 508         reg = readl(&mxc_ccm->chsccdr);
 509         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 510                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 511         writel(reg, &mxc_ccm->chsccdr);
 512
 513         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 514              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 515              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 516              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 517              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 518              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 519              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 520              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 521              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 522         writel(reg, &iomux->gpr[2]);
 523
 524         reg = readl(&iomux->gpr[3]);
 525         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 526             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 527                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 528         writel(reg, &iomux->gpr[3]);
 529
 530         /* Backlight CABEN on LVDS connector */
 531         SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
 532         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 533 }
 534 #endif /* CONFIG_VIDEO_IPUV3 */
 535
 536 /*
 537  * Baseboard specific GPIO
 538  */
 539
 540 /* common to add baseboards */
 541 static iomux_v3_cfg_t const gw_gpio_pads[] = {
 542         /* MSATA_EN */
 543         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
 544         /* RS232_EN# */
 545         IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
 546 };
 547
 548 /* prototype */
 549 static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
 550         /* PANLEDG# */
 551         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 552         /* PANLEDR# */
 553         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 554         /* LOCLED# */
 555         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 556         /* RS485_EN */
 557         IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
 558         /* IOEXP_PWREN# */
 559         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 560         /* IOEXP_IRQ# */
 561         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 562         /* VID_EN */
 563         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 564         /* DIOI2C_DIS# */
 565         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 566         /* PCICK_SSON */
 567         IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
 568         /* PCI_RST# */
 569         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 570 };
 571
 572 static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
 573         /* PANLEDG# */
 574         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 575         /* PANLEDR# */
 576         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 577         /* IOEXP_PWREN# */
 578         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 579         /* IOEXP_IRQ# */
 580         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 581
 582         /* GPS_SHDN */
 583         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 584         /* VID_PWR */
 585         IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
 586         /* PCI_RST# */
 587         IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
 588         /* PCIESKT_WDIS# */
 589         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 590 };
 591
 592 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
 593         /* PANLEDG# */
 594         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 595         /* PANLEDR# */
 596         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 597         /* IOEXP_PWREN# */
 598         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 599         /* IOEXP_IRQ# */
 600         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 601
 602         /* MX6_LOCLED# */
 603         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 604         /* GPS_SHDN */
 605         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
 606         /* USBOTG_SEL */
 607         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 608         /* VID_PWR */
 609         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 610         /* PCI_RST# */
 611         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 612         /* PCIESKT_WDIS# */
 613         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 614 };
 615
 616 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
 617         /* PANLEDG# */
 618         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 619         /* PANLEDR# */
 620         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 621         /* IOEXP_PWREN# */
 622         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 623         /* IOEXP_IRQ# */
 624         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 625         /* DIOI2C_DIS# */
 626         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 627
 628         /* MX6_LOCLED# */
 629         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 630         /* GPS_SHDN */
 631         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
 632         /* VID_EN */
 633         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 634         /* PCI_RST# */
 635         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 636         /* PCIESKT_WDIS# */
 637         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 638 };
 639
 640 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
 641         /* PANLEDG# */
 642         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 643         /* PANLEDR# */
 644         IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
 645         /* MX6_LOCLED# */
 646         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 647         /* MIPI_DIO */
 648         IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG),
 649         /* RS485_EN */
 650         IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG),
 651         /* IOEXP_PWREN# */
 652         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 653         /* IOEXP_IRQ# */
 654         IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 655         /* DIOI2C_DIS# */
 656         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 657         /* PCICK_SSON */
 658         IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
 659         /* PCI_RST# */
 660         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 661         /* VID_EN */
 662         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 663         /* PCIESKT_WDIS# */
 664         IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
 665 };
 666
 667 /*
 668  * each baseboard has 4 user configurable Digital IO lines which can
 669  * be pinmuxed as a GPIO or in some cases a PWM
 670  */
 671 struct dio_cfg {
 672         iomux_v3_cfg_t gpio_padmux[2];
 673         unsigned gpio_param;
 674         iomux_v3_cfg_t pwm_padmux[2];
 675         unsigned pwm_param;
 676 };
 677
 678 struct ventana {
 679         /* pinmux */
 680         iomux_v3_cfg_t const *gpio_pads;
 681         int num_pads;
 682         /* DIO pinmux/val */
 683         struct dio_cfg dio_cfg[4];
 684         /* various gpios (0 if non-existent) */
 685         int leds[3];
 686         int pcie_rst;
 687         int mezz_pwren;
 688         int mezz_irq;
 689         int rs485en;
 690         int gps_shdn;
 691         int vidin_en;
 692         int dioi2c_en;
 693         int pcie_sson;
 694         int usb_sel;
 695         int wdis;
 696 };
 697
 698 struct ventana gpio_cfg[] = {
 699         /* GW5400proto */
 700         {
 701                 .gpio_pads = gw54xx_gpio_pads,
 702                 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
 703                 .dio_cfg = {
 704                         {
 705                                 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
 706                                 IMX_GPIO_NR(1, 9),
 707                                 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
 708                                 1
 709                         },
 710                         {
 711                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 712                                 IMX_GPIO_NR(1, 19),
 713                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 714                                 2
 715                         },
 716                         {
 717                                 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
 718                                 IMX_GPIO_NR(2, 9),
 719                                 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
 720                                 3
 721                         },
 722                         {
 723                                 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
 724                                 IMX_GPIO_NR(2, 10),
 725                                 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
 726                                 4
 727                         },
 728                 },
 729                 .leds = {
 730                         IMX_GPIO_NR(4, 6),
 731                         IMX_GPIO_NR(4, 10),
 732                         IMX_GPIO_NR(4, 15),
 733                 },
 734                 .pcie_rst = IMX_GPIO_NR(1, 29),
 735                 .mezz_pwren = IMX_GPIO_NR(4, 7),
 736                 .mezz_irq = IMX_GPIO_NR(4, 9),
 737                 .rs485en = IMX_GPIO_NR(3, 24),
 738                 .dioi2c_en = IMX_GPIO_NR(4,  5),
 739                 .pcie_sson = IMX_GPIO_NR(1, 20),
 740         },
 741
 742         /* GW51xx */
 743         {
 744                 .gpio_pads = gw51xx_gpio_pads,
 745                 .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
 746                 .dio_cfg = {
 747                         {
 748                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 749                                 IMX_GPIO_NR(1, 16),
 750                                 { 0, 0 },
 751                                 0
 752                         },
 753                         {
 754                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 755                                 IMX_GPIO_NR(1, 19),
 756                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 757                                 2
 758                         },
 759                         {
 760                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 761                                 IMX_GPIO_NR(1, 17),
 762                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 763                                 3
 764                         },
 765                         {
 766                                 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
 767                                 IMX_GPIO_NR(1, 18),
 768                                 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
 769                                 4
 770                         },
 771                 },
 772                 .leds = {
 773                         IMX_GPIO_NR(4, 6),
 774                         IMX_GPIO_NR(4, 10),
 775                 },
 776                 .pcie_rst = IMX_GPIO_NR(1, 0),
 777                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 778                 .mezz_irq = IMX_GPIO_NR(2, 18),
 779                 .gps_shdn = IMX_GPIO_NR(1, 2),
 780                 .vidin_en = IMX_GPIO_NR(5, 20),
 781                 .wdis = IMX_GPIO_NR(7, 12),
 782         },
 783
 784         /* GW52xx */
 785         {
 786                 .gpio_pads = gw52xx_gpio_pads,
 787                 .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
 788                 .dio_cfg = {
 789                         {
 790                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 791                                 IMX_GPIO_NR(1, 16),
 792                                 { 0, 0 },
 793                                 0
 794                         },
 795                         {
 796                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 797                                 IMX_GPIO_NR(1, 19),
 798                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 799                                 2
 800                         },
 801                         {
 802                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 803                                 IMX_GPIO_NR(1, 17),
 804                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 805                                 3
 806                         },
 807                         {
 808                                 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
 809                                 IMX_GPIO_NR(1, 20),
 810                                 { 0, 0 },
 811                                 0
 812                         },
 813                 },
 814                 .leds = {
 815                         IMX_GPIO_NR(4, 6),
 816                         IMX_GPIO_NR(4, 7),
 817                         IMX_GPIO_NR(4, 15),
 818                 },
 819                 .pcie_rst = IMX_GPIO_NR(1, 29),
 820                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 821                 .mezz_irq = IMX_GPIO_NR(2, 18),
 822                 .gps_shdn = IMX_GPIO_NR(1, 27),
 823                 .vidin_en = IMX_GPIO_NR(3, 31),
 824                 .usb_sel = IMX_GPIO_NR(1, 2),
 825                 .wdis = IMX_GPIO_NR(7, 12),
 826         },
 827
 828         /* GW53xx */
 829         {
 830                 .gpio_pads = gw53xx_gpio_pads,
 831                 .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
 832                 .dio_cfg = {
 833                         {
 834                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 835                                 IMX_GPIO_NR(1, 16),
 836                                 { 0, 0 },
 837                                 0
 838                         },
 839                         {
 840                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 841                                 IMX_GPIO_NR(1, 19),
 842                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 843                                 2
 844                         },
 845                         {
 846                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 847                                 IMX_GPIO_NR(1, 17),
 848                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 849                                 3
 850                         },
 851                         {
 852                                 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
 853                                 IMX_GPIO_NR(1, 20),
 854                                 { 0, 0 },
 855                                 0
 856                         },
 857                 },
 858                 .leds = {
 859                         IMX_GPIO_NR(4, 6),
 860                         IMX_GPIO_NR(4, 7),
 861                         IMX_GPIO_NR(4, 15),
 862                 },
 863                 .pcie_rst = IMX_GPIO_NR(1, 29),
 864                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 865                 .mezz_irq = IMX_GPIO_NR(2, 18),
 866                 .gps_shdn = IMX_GPIO_NR(1, 27),
 867                 .vidin_en = IMX_GPIO_NR(3, 31),
 868                 .wdis = IMX_GPIO_NR(7, 12),
 869         },
 870
 871         /* GW54xx */
 872         {
 873                 .gpio_pads = gw54xx_gpio_pads,
 874                 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
 875                 .dio_cfg = {
 876                         {
 877                                 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
 878                                 IMX_GPIO_NR(1, 9),
 879                                 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
 880                                 1
 881                         },
 882                         {
 883                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 884                                 IMX_GPIO_NR(1, 19),
 885                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 886                                 2
 887                         },
 888                         {
 889                                 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
 890                                 IMX_GPIO_NR(2, 9),
 891                                 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
 892                                 3
 893                         },
 894                         {
 895                                 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
 896                                 IMX_GPIO_NR(2, 10),
 897                                 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
 898                                 4
 899                         },
 900                 },
 901                 .leds = {
 902                         IMX_GPIO_NR(4, 6),
 903                         IMX_GPIO_NR(4, 7),
 904                         IMX_GPIO_NR(4, 15),
 905                 },
 906                 .pcie_rst = IMX_GPIO_NR(1, 29),
 907                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 908                 .mezz_irq = IMX_GPIO_NR(2, 18),
 909                 .rs485en = IMX_GPIO_NR(7, 1),
 910                 .vidin_en = IMX_GPIO_NR(3, 31),
 911                 .dioi2c_en = IMX_GPIO_NR(4,  5),
 912                 .pcie_sson = IMX_GPIO_NR(1, 20),
 913                 .wdis = IMX_GPIO_NR(5, 17),
 914         },
 915 };
 916
 917 /* setup board specific PMIC */
 918 int power_init_board(void)
 919 {
 920         struct pmic *p;
 921         u32 reg;
 922
 923         /* configure PFUZE100 PMIC */
 924         if (board_type == GW54xx || board_type == GW54proto) {
 925                 power_pfuze100_init(I2C_PMIC);
 926                 p = pmic_get("PFUZE100");
 927                 if (p && !pmic_probe(p)) {
 928                         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 929                         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 930
 931                         /* Set VGEN1 to 1.5V and enable */
 932                         pmic_reg_read(p, PFUZE100_VGEN1VOL, &reg);
 933                         reg &= ~(LDO_VOL_MASK);
 934                         reg |= (LDOA_1_50V | LDO_EN);
 935                         pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
 936
 937                         /* Set SWBST to 5.0V and enable */
 938                         pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
 939                         reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
 940                         reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
 941                         pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
 942                 }
 943         }
 944
 945         /* configure LTC3676 PMIC */
 946         else {
 947                 power_ltc3676_init(I2C_PMIC);
 948                 p = pmic_get("LTC3676_PMIC");
 949                 if (p && !pmic_probe(p)) {
 950                         puts("PMIC:  LTC3676\n");
 951                         /* set board-specific scalar to 1225mV for IMX6Q@1GHz */
 952                         if (is_cpu_type(MXC_CPU_MX6Q)) {
 953                                 /* mask PGOOD during SW1 transition */
 954                                 reg = 0x1d | LTC3676_PGOOD_MASK;
 955                                 pmic_reg_write(p, LTC3676_DVB1B, reg);
 956                                 /* set SW1 (VDD_SOC) to 1259mV */
 957                                 reg = 0x1d;
 958                                 pmic_reg_write(p, LTC3676_DVB1A, reg);
 959
 960                                 /* mask PGOOD during SW3 transition */
 961                                 reg = 0x1d | LTC3676_PGOOD_MASK;
 962                                 pmic_reg_write(p, LTC3676_DVB3B, reg);
 963                                 /*set SW3 (VDD_ARM) to 1259mV */
 964                                 reg = 0x1d;
 965                                 pmic_reg_write(p, LTC3676_DVB3A, reg);
 966                         }
 967                 }
 968         }
 969
 970         return 0;
 971 }
 972
 973 /* setup GPIO pinmux and default configuration per baseboard */
 974 static void setup_board_gpio(int board)
 975 {
 976         struct ventana_board_info *info = &ventana_info;
 977         const char *s;
 978         char arg[10];
 979         size_t len;
 980         int i;
 981         int quiet = simple_strtol(getenv("quiet"), NULL, 10);
 982
 983         if (board >= GW_UNKNOWN)
 984                 return;
 985
 986         /* RS232_EN# */
 987         gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
 988
 989         /* MSATA Enable */
 990         if (is_cpu_type(MXC_CPU_MX6Q) &&
 991             test_bit(EECONFIG_SATA, info->config)) {
 992                 gpio_direction_output(GP_MSATA_SEL,
 993                                       (hwconfig("msata")) ?  1 : 0);
 994         } else {
 995                 gpio_direction_output(GP_MSATA_SEL, 0);
 996         }
 997
 998         /*
 999          * assert PCI_RST# (released by OS when clock is valid)
1000          * TODO: figure out why leaving this de-asserted from PCI scan on boot
1001          *       causes linux pcie driver to hang during enumeration
1002          */
1003         gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
1004
1005         /* turn off (active-high) user LED's */
1006         for (i = 0; i < 4; i++) {
1007                 if (gpio_cfg[board].leds[i])
1008                         gpio_direction_output(gpio_cfg[board].leds[i], 1);
1009         }
1010
1011         /* Expansion Mezzanine IO */
1012         gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
1013         gpio_direction_input(gpio_cfg[board].mezz_irq);
1014
1015         /* RS485 Transmit Enable */
1016         if (gpio_cfg[board].rs485en)
1017                 gpio_direction_output(gpio_cfg[board].rs485en, 0);
1018
1019         /* GPS_SHDN */
1020         if (gpio_cfg[board].gps_shdn)
1021                 gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
1022
1023         /* Analog video codec power enable */
1024         if (gpio_cfg[board].vidin_en)
1025                 gpio_direction_output(gpio_cfg[board].vidin_en, 1);
1026
1027         /* DIOI2C_DIS# */
1028         if (gpio_cfg[board].dioi2c_en)
1029                 gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
1030
1031         /* PCICK_SSON: disable spread-spectrum clock */
1032         if (gpio_cfg[board].pcie_sson)
1033                 gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
1034
1035         /* USBOTG Select (PCISKT or FrontPanel) */
1036         if (gpio_cfg[board].usb_sel)
1037                 gpio_direction_output(gpio_cfg[board].usb_sel, 0);
1038
1039         /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
1040         if (gpio_cfg[board].wdis)
1041                 gpio_direction_output(gpio_cfg[board].wdis, 1);
1042
1043         /*
1044          * Configure DIO pinmux/padctl registers
1045          * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
1046          */
1047         for (i = 0; i < 4; i++) {
1048                 struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
1049                 iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
1050                 unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
1051
1052                 sprintf(arg, "dio%d", i);
1053                 if (!hwconfig(arg))
1054                         continue;
1055                 s = hwconfig_subarg(arg, "padctrl", &len);
1056                 if (s) {
1057                         ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16)
1058                                             & 0x1ffff) | MUX_MODE_SION;
1059                 }
1060                 if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
1061                         if (!quiet) {
1062                                 printf("DIO%d:  GPIO%d_IO%02d (gpio-%d)\n", i,
1063                                        (cfg->gpio_param/32)+1,
1064                                        cfg->gpio_param%32,
1065                                        cfg->gpio_param);
1066                         }
1067                         imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
1068                                                ctrl);
1069                         gpio_direction_input(cfg->gpio_param);
1070                 } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
1071                            cfg->pwm_padmux) {
1072                         if (!quiet)
1073                                 printf("DIO%d:  pwm%d\n", i, cfg->pwm_param);
1074                         imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
1075                                                MUX_PAD_CTRL(ctrl));
1076                 }
1077         }
1078
1079         if (!quiet) {
1080                 if (is_cpu_type(MXC_CPU_MX6Q) &&
1081                     (test_bit(EECONFIG_SATA, info->config))) {
1082                         printf("MSATA: %s\n", (hwconfig("msata") ?
1083                                "enabled" : "disabled"));
1084                 }
1085                 printf("RS232: %s\n", (hwconfig("rs232")) ?
1086                        "enabled" : "disabled");
1087         }
1088 }
1089
1090 #if defined(CONFIG_CMD_PCI)
1091 int imx6_pcie_toggle_reset(void)
1092 {
1093         if (board_type < GW_UNKNOWN) {
1094                 uint pin = gpio_cfg[board_type].pcie_rst;
1095                 gpio_direction_output(pin, 0);
1096                 mdelay(50);
1097                 gpio_direction_output(pin, 1);
1098         }
1099         return 0;
1100 }
1101 #endif /* CONFIG_CMD_PCI */
1102
1103 #ifdef CONFIG_SERIAL_TAG
1104 /*
1105  * called when setting up ATAGS before booting kernel
1106  * populate serialnum from the following (in order of priority):
1107  *   serial# env var
1108  *   eeprom
1109  */
1110 void get_board_serial(struct tag_serialnr *serialnr)
1111 {
1112         char *serial = getenv("serial#");
1113
1114         if (serial) {
1115                 serialnr->high = 0;
1116                 serialnr->low = simple_strtoul(serial, NULL, 10);
1117         } else if (ventana_info.model[0]) {
1118                 serialnr->high = 0;
1119                 serialnr->low = ventana_info.serial;
1120         } else {
1121                 serialnr->high = 0;
1122                 serialnr->low = 0;
1123         }
1124 }
1125 #endif
1126
1127 /*
1128  * Board Support
1129  */
1130
1131 /* called from SPL board_init_f() */
1132 int board_early_init_f(void)
1133 {
1134         setup_iomux_uart();
1135         gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
1136
1137 #if defined(CONFIG_VIDEO_IPUV3)
1138         setup_display();
1139 #endif
1140         return 0;
1141 }
1142
1143 int dram_init(void)
1144 {
1145         gd->ram_size = imx_ddr_size();
1146         return 0;
1147 }
1148
1149 int board_init(void)
1150 {
1151         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
1152
1153         clrsetbits_le32(&iomuxc_regs->gpr[1],
1154                         IOMUXC_GPR1_OTG_ID_MASK,
1155                         IOMUXC_GPR1_OTG_ID_GPIO1);
1156
1157         /* address of linux boot parameters */
1158         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
1159
1160 #ifdef CONFIG_CMD_NAND
1161         setup_gpmi_nand();
1162 #endif
1163 #ifdef CONFIG_MXC_SPI
1164         setup_spi();
1165 #endif
1166         if (is_cpu_type(MXC_CPU_MX6Q)) {
1167                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
1168                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
1169                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
1170         } else {
1171                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
1172                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
1173                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
1174         }
1175
1176 #ifdef CONFIG_CMD_SATA
1177         setup_sata();
1178 #endif
1179         /* read Gateworks EEPROM into global struct (used later) */
1180         board_type = read_eeprom(I2C_GSC, &ventana_info);
1181
1182         /* board-specifc GPIO iomux */
1183         SETUP_IOMUX_PADS(gw_gpio_pads);
1184         if (board_type < GW_UNKNOWN) {
1185                 iomux_v3_cfg_t const *p = gpio_cfg[board_type].gpio_pads;
1186                 int count = gpio_cfg[board_type].num_pads;
1187
1188                 imx_iomux_v3_setup_multiple_pads(p, count);
1189         }
1190
1191         return 0;
1192 }
1193
1194 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
1195 /*
1196  * called during late init (after relocation and after board_init())
1197  * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
1198  * EEPROM read.
1199  */
1200 int checkboard(void)
1201 {
1202         struct ventana_board_info *info = &ventana_info;
1203         unsigned char buf[4];
1204         const char *p;
1205         int quiet; /* Quiet or minimal output mode */
1206
1207         quiet = 0;
1208         p = getenv("quiet");
1209         if (p)
1210                 quiet = simple_strtol(p, NULL, 10);
1211         else
1212                 setenv("quiet", "0");
1213
1214         puts("\nGateworks Corporation Copyright 2014\n");
1215         if (info->model[0]) {
1216                 printf("Model: %s\n", info->model);
1217                 printf("MFGDate: %02x-%02x-%02x%02x\n",
1218                        info->mfgdate[0], info->mfgdate[1],
1219                        info->mfgdate[2], info->mfgdate[3]);
1220                 printf("Serial:%d\n", info->serial);
1221         } else {
1222                 puts("Invalid EEPROM - board will not function fully\n");
1223         }
1224         if (quiet)
1225                 return 0;
1226
1227         /* Display GSC firmware revision/CRC/status */
1228         i2c_set_bus_num(I2C_GSC);
1229         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) {
1230                 printf("GSC:   v%d", buf[0]);
1231                 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) {
1232                         printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */
1233                         printf(" 0x%02x", buf[0]); /* irq status */
1234                 }
1235                 puts("\n");
1236         }
1237         /* Display RTC */
1238         if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
1239                 printf("RTC:   %d\n",
1240                        buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
1241         }
1242
1243         return 0;
1244 }
1245 #endif
1246
1247 #ifdef CONFIG_CMD_BMODE
1248 /*
1249  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
1250  * see Table 8-11 and Table 5-9
1251  *  BOOT_CFG1[7] = 1 (boot from NAND)
1252  *  BOOT_CFG1[5] = 0 - raw NAND
1253  *  BOOT_CFG1[4] = 0 - default pad settings
1254  *  BOOT_CFG1[3:2] = 00 - devices = 1
1255  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
1256  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
1257  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
1258  *  BOOT_CFG2[0] = 0 - Reset time 12ms
1259  */
1260 static const struct boot_mode board_boot_modes[] = {
1261         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
1262         { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
1263         { NULL, 0 },
1264 };
1265 #endif
1266
1267 /* late init */
1268 int misc_init_r(void)
1269 {
1270         struct ventana_board_info *info = &ventana_info;
1271         unsigned char reg;
1272
1273         /* set env vars based on EEPROM data */
1274         if (ventana_info.model[0]) {
1275                 char str[16], fdt[36];
1276                 char *p;
1277                 const char *cputype = "";
1278                 int i;
1279
1280                 /*
1281                  * FDT name will be prefixed with CPU type.  Three versions
1282                  * will be created each increasingly generic and bootloader
1283                  * env scripts will try loading each from most specific to
1284                  * least.
1285                  */
1286                 if (is_cpu_type(MXC_CPU_MX6Q) ||
1287                     is_cpu_type(MXC_CPU_MX6D))
1288                         cputype = "imx6q";
1289                 else if (is_cpu_type(MXC_CPU_MX6DL) ||
1290                          is_cpu_type(MXC_CPU_MX6SOLO))
1291                         cputype = "imx6dl";
1292                 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
1293                         setenv("flash_layout", "large");
1294                 else
1295                         setenv("flash_layout", "normal");
1296                 memset(str, 0, sizeof(str));
1297                 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
1298                         str[i] = tolower(info->model[i]);
1299                 if (!getenv("model"))
1300                         setenv("model", str);
1301                 if (!getenv("fdt_file")) {
1302                         sprintf(fdt, "%s-%s.dtb", cputype, str);
1303                         setenv("fdt_file", fdt);
1304                 }
1305                 p = strchr(str, '-');
1306                 if (p) {
1307                         *p++ = 0;
1308
1309                         setenv("model_base", str);
1310                         if (!getenv("fdt_file1")) {
1311                                 sprintf(fdt, "%s-%s.dtb", cputype, str);
1312                                 setenv("fdt_file1", fdt);
1313                         }
1314                         str[4] = 'x';
1315                         str[5] = 'x';
1316                         str[6] = 0;
1317                         if (!getenv("fdt_file2")) {
1318                                 sprintf(fdt, "%s-%s.dtb", cputype, str);
1319                                 setenv("fdt_file2", fdt);
1320                         }
1321                 }
1322
1323                 /* initialize env from EEPROM */
1324                 if (test_bit(EECONFIG_ETH0, info->config) &&
1325                     !getenv("ethaddr")) {
1326                         eth_setenv_enetaddr("ethaddr", info->mac0);
1327                 }
1328                 if (test_bit(EECONFIG_ETH1, info->config) &&
1329                     !getenv("eth1addr")) {
1330                         eth_setenv_enetaddr("eth1addr", info->mac1);
1331                 }
1332
1333                 /* board serial-number */
1334                 sprintf(str, "%6d", info->serial);
1335                 setenv("serial#", str);
1336         }
1337
1338
1339         /* setup baseboard specific GPIO pinmux and config */
1340         setup_board_gpio(board_type);
1341
1342 #ifdef CONFIG_CMD_BMODE
1343         add_board_boot_modes(board_boot_modes);
1344 #endif
1345
1346         /*
1347          *  The Gateworks System Controller implements a boot
1348          *  watchdog (always enabled) as a workaround for IMX6 boot related
1349          *  errata such as:
1350          *    ERR005768 - no fix
1351          *    ERR006282 - fixed in silicon r1.3
1352          *    ERR007117 - fixed in silicon r1.3
1353          *    ERR007220 - fixed in silicon r1.3
1354          *  see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
1355          *
1356          * Disable the boot watchdog and display/clear the timeout flag if set
1357          */
1358         i2c_set_bus_num(I2C_GSC);
1359         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) {
1360                 reg |= (1 << GSC_SC_CTRL1_WDDIS);
1361                 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
1362                         puts("Error: could not disable GSC Watchdog\n");
1363         } else {
1364                 puts("Error: could not disable GSC Watchdog\n");
1365         }
1366         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1)) {
1367                 if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */
1368                         puts("GSC boot watchdog timeout detected\n");
1369                         reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */
1370                         gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1);
1371                 }
1372         }
1373
1374         return 0;
1375 }
1376
1377 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1378
1379 /* FDT aliases associated with EEPROM config bits */
1380 const char *fdt_aliases[] = {
1381         "ethernet0",
1382         "ethernet1",
1383         "hdmi_out",
1384         "ahci0",
1385         "pcie",
1386         "ssi0",
1387         "ssi1",
1388         "lcd0",
1389         "lvds0",
1390         "lvds1",
1391         "usb0",
1392         "usb1",
1393         "mmc0",
1394         "mmc1",
1395         "mmc2",
1396         "mmc3",
1397         "uart0",
1398         "uart1",
1399         "uart2",
1400         "uart3",
1401         "uart4",
1402         "ipu0",
1403         "ipu1",
1404         "can0",
1405         "mipi_dsi",
1406         "mipi_csi",
1407         "tzasc0",
1408         "tzasc1",
1409         "i2c0",
1410         "i2c1",
1411         "i2c2",
1412         "vpu",
1413         "csi0",
1414         "csi1",
1415         NULL,
1416         NULL,
1417         NULL,
1418         NULL,
1419         NULL,
1420         NULL,
1421         "spi0",
1422         "spi1",
1423         "spi2",
1424         "spi3",
1425         "spi4",
1426         "spi5",
1427         NULL,
1428         NULL,
1429         "pps",
1430         NULL,
1431         NULL,
1432         NULL,
1433         "hdmi_in",
1434         "cvbs_out",
1435         "cvbs_in",
1436         "nand",
1437         NULL,
1438         NULL,
1439         NULL,
1440         NULL,
1441         NULL,
1442         NULL,
1443         NULL,
1444         NULL,
1445 };
1446
1447 /*
1448  * called prior to booting kernel or by 'fdt boardsetup' command
1449  *
1450  * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1451  *  - mtd partitions based on mtdparts/mtdids env
1452  *  - system-serial (board serial num from EEPROM)
1453  *  - board (full model from EEPROM)
1454  *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
1455  */
1456 void ft_board_setup(void *blob, bd_t *bd)
1457 {
1458         int bit;
1459         struct ventana_board_info *info = &ventana_info;
1460         struct node_info nodes[] = {
1461                 { "sst,w25q256",          MTD_DEV_TYPE_NOR, },  /* SPI flash */
1462                 { "fsl,imx6q-gpmi-nand",  MTD_DEV_TYPE_NAND, }, /* NAND flash */
1463         };
1464         const char *model = getenv("model");
1465
1466         if (getenv("fdt_noauto")) {
1467                 puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
1468                 return;
1469         }
1470
1471         /* Update partition nodes using info from mtdparts env var */
1472         puts("   Updating MTD partitions...\n");
1473         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1474
1475         if (!model) {
1476                 puts("invalid board info: Leaving FDT fully enabled\n");
1477                 return;
1478         }
1479         printf("   Adjusting FDT per EEPROM for %s...\n", model);
1480
1481         /* board serial number */
1482         fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
1483                     strlen(getenv("serial#")) + 1);
1484
1485         /* board (model contains model from device-tree) */
1486         fdt_setprop(blob, 0, "board", info->model,
1487                     strlen((const char *)info->model) + 1);
1488
1489         /*
1490          * Peripheral Config:
1491          *  remove nodes by alias path if EEPROM config tells us the
1492          *  peripheral is not loaded on the board.
1493          */
1494         for (bit = 0; bit < 64; bit++) {
1495                 if (!test_bit(bit, info->config))
1496                         fdt_del_node_and_alias(blob, fdt_aliases[bit]);
1497         }
1498 }
1499 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
1500