2 * Copyright (C) 2013 Gateworks Corporation
4 * Author: Tim Harvey <tharvey@gateworks.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/mxc_hdmi.h>
15 #include <asm/arch/sys_proto.h>
17 #include <asm/imx-common/boot_mode.h>
18 #include <asm/imx-common/sata.h>
19 #include <asm/imx-common/spi.h>
20 #include <asm/imx-common/video.h>
23 #include <dm/platform_data/serial_mxc.h>
26 #include <fdt_support.h>
27 #include <fsl_esdhc.h>
28 #include <jffs2/load_kernel.h>
29 #include <linux/ctype.h>
34 #include <power/pmic.h>
35 #include <power/ltc3676_pmic.h>
36 #include <power/pfuze100_pmic.h>
37 #include <fdt_support.h>
38 #include <jffs2/load_kernel.h>
39 #include <spi_flash.h>
44 DECLARE_GLOBAL_DATA_PTR;
48 * EEPROM board info struct populated by read_eeprom so that we only have to
51 struct ventana_board_info ventana_info;
53 static int board_type;
56 static iomux_v3_cfg_t const usdhc3_pads[] = {
57 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
58 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
59 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
60 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
61 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
62 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
63 IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
67 static iomux_v3_cfg_t const enet_pads[] = {
68 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
69 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
70 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
71 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
72 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
73 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
74 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
75 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
76 MUX_PAD_CTRL(ENET_PAD_CTRL)),
77 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
78 MUX_PAD_CTRL(ENET_PAD_CTRL)),
79 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
80 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
81 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
82 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
83 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
84 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
85 MUX_PAD_CTRL(ENET_PAD_CTRL)),
87 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
91 static iomux_v3_cfg_t const nfc_pads[] = {
92 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
93 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
94 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
95 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
96 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
97 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
98 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
99 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
100 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
101 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
102 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
103 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
104 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
105 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
106 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
109 #ifdef CONFIG_CMD_NAND
110 static void setup_gpmi_nand(void)
112 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
114 /* config gpmi nand iomux */
115 SETUP_IOMUX_PADS(nfc_pads);
117 /* config gpmi and bch clock to 100 MHz */
118 clrsetbits_le32(&mxc_ccm->cs2cdr,
119 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
120 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
121 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
122 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
123 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
124 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
126 /* enable gpmi and bch clock gating */
127 setbits_le32(&mxc_ccm->CCGR4,
128 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
129 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
130 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
131 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
132 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
134 /* enable apbh clock gating */
135 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
139 static void setup_iomux_enet(int gpio)
141 SETUP_IOMUX_PADS(enet_pads);
143 /* toggle PHY_RST# */
144 gpio_request(gpio, "phy_rst#");
145 gpio_direction_output(gpio, 0);
147 gpio_set_value(gpio, 1);
150 #ifdef CONFIG_USB_EHCI_MX6
151 static iomux_v3_cfg_t const usb_pads[] = {
152 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
153 IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
155 IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
158 int board_ehci_hcd_init(int port)
162 SETUP_IOMUX_PADS(usb_pads);
165 switch (board_type) {
168 gpio = (IMX_GPIO_NR(1, 9));
172 gpio = (IMX_GPIO_NR(1, 16));
178 /* request and toggle hub rst */
179 gpio_request(gpio, "usb_hub_rst#");
180 gpio_direction_output(gpio, 0);
182 gpio_set_value(gpio, 1);
187 int board_ehci_power(int port, int on)
191 gpio_set_value(GP_USB_OTG_PWR, on);
194 #endif /* CONFIG_USB_EHCI_MX6 */
196 #ifdef CONFIG_FSL_ESDHC
197 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
199 int board_mmc_getcd(struct mmc *mmc)
202 gpio_request(GP_SD3_CD, "sd_cd");
203 gpio_direction_input(GP_SD3_CD);
204 return !gpio_get_value(GP_SD3_CD);
207 int board_mmc_init(bd_t *bis)
209 /* Only one USDHC controller on Ventana */
210 SETUP_IOMUX_PADS(usdhc3_pads);
211 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
212 usdhc_cfg.max_bus_width = 4;
214 return fsl_esdhc_initialize(bis, &usdhc_cfg);
216 #endif /* CONFIG_FSL_ESDHC */
218 #ifdef CONFIG_MXC_SPI
219 iomux_v3_cfg_t const ecspi1_pads[] = {
221 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
222 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
223 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
224 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
227 int board_spi_cs_gpio(unsigned bus, unsigned cs)
229 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
232 static void setup_spi(void)
234 gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
235 gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
236 SETUP_IOMUX_PADS(ecspi1_pads);
240 /* configure eth0 PHY board-specific LED behavior */
241 int board_phy_config(struct phy_device *phydev)
246 if (phydev->phy_id == 0x1410dd1) {
248 * Page 3, Register 16: LED[2:0] Function Control Register
249 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
250 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
252 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
253 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
256 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
257 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
260 if (phydev->drv->config)
261 phydev->drv->config(phydev);
266 int board_eth_init(bd_t *bis)
268 #ifdef CONFIG_FEC_MXC
269 struct ventana_board_info *info = &ventana_info;
271 if (test_bit(EECONFIG_ETH0, info->config)) {
272 setup_iomux_enet(GP_PHY_RST);
278 e1000_initialize(bis);
282 /* For otg ethernet*/
283 usb_eth_initialize(bis);
286 /* default to the first detected enet dev */
287 if (!getenv("ethprime")) {
288 struct eth_device *dev = eth_get_dev_by_index(0);
290 setenv("ethprime", dev->name);
291 printf("set ethprime to %s\n", getenv("ethprime"));
298 #if defined(CONFIG_VIDEO_IPUV3)
300 static void enable_hdmi(struct display_info_t const *dev)
302 imx_enable_hdmi_phy();
305 static int detect_i2c(struct display_info_t const *dev)
307 return i2c_set_bus_num(dev->bus) == 0 &&
308 i2c_probe(dev->addr) == 0;
311 static void enable_lvds(struct display_info_t const *dev)
313 struct iomuxc *iomux = (struct iomuxc *)
316 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
317 u32 reg = readl(&iomux->gpr[2]);
318 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
319 writel(reg, &iomux->gpr[2]);
321 /* Enable Backlight */
322 gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
323 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
324 gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
325 SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
326 gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
329 struct display_info_t const displays[] = {{
333 .pixfmt = IPU_PIX_FMT_RGB24,
334 .detect = detect_hdmi,
335 .enable = enable_hdmi,
349 .vmode = FB_VMODE_NONINTERLACED
351 /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
354 .pixfmt = IPU_PIX_FMT_LVDS666,
355 .detect = detect_i2c,
356 .enable = enable_lvds,
358 .name = "Hannstar-XGA",
370 .vmode = FB_VMODE_NONINTERLACED
376 .enable = enable_lvds,
377 .pixfmt = IPU_PIX_FMT_LVDS666,
379 .name = "DLC700JMGT4",
381 .xres = 1024, /* 1024x600active pixels */
383 .pixclock = 15385, /* 64MHz */
391 .vmode = FB_VMODE_NONINTERLACED
397 .enable = enable_lvds,
398 .pixfmt = IPU_PIX_FMT_LVDS666,
400 .name = "DLC800FIGT3",
402 .xres = 1024, /* 1024x768 active pixels */
404 .pixclock = 15385, /* 64MHz */
412 .vmode = FB_VMODE_NONINTERLACED
414 size_t display_count = ARRAY_SIZE(displays);
416 static void setup_display(void)
418 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
419 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
424 /* Turn on LDB0,IPU,IPU DI0 clocks */
425 reg = __raw_readl(&mxc_ccm->CCGR3);
426 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
427 writel(reg, &mxc_ccm->CCGR3);
429 /* set LDB0, LDB1 clk select to 011/011 */
430 reg = readl(&mxc_ccm->cs2cdr);
431 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
432 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
433 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
434 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
435 writel(reg, &mxc_ccm->cs2cdr);
437 reg = readl(&mxc_ccm->cscmr2);
438 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
439 writel(reg, &mxc_ccm->cscmr2);
441 reg = readl(&mxc_ccm->chsccdr);
442 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
443 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
444 writel(reg, &mxc_ccm->chsccdr);
446 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
447 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
448 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
449 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
450 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
451 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
452 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
453 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
454 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
455 writel(reg, &iomux->gpr[2]);
457 reg = readl(&iomux->gpr[3]);
458 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
459 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
460 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
461 writel(reg, &iomux->gpr[3]);
463 /* LVDS Backlight GPIO on LVDS connector - output low */
464 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
465 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
467 #endif /* CONFIG_VIDEO_IPUV3 */
469 /* setup board specific PMIC */
470 int power_init_board(void)
476 #if defined(CONFIG_CMD_PCI)
477 int imx6_pcie_toggle_reset(void)
479 if (board_type < GW_UNKNOWN) {
480 uint pin = gpio_cfg[board_type].pcie_rst;
481 gpio_request(pin, "pci_rst#");
482 gpio_direction_output(pin, 0);
484 gpio_direction_output(pin, 1);
490 * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
491 * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
492 * properly and assert reset for 100ms.
494 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
495 unsigned short vendor, unsigned short device,
496 unsigned short class)
500 debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
501 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
502 if (vendor == PCI_VENDOR_ID_PLX &&
503 (device & 0xfff0) == 0x8600 &&
504 PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
505 debug("configuring PLX 860X downstream PERST#\n");
506 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
507 dw |= 0xaaa8; /* GPIO1-7 outputs */
508 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
510 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
511 dw |= 0xfe; /* GPIO1-7 output high */
512 pci_hose_write_config_dword(hose, dev, 0x644, dw);
517 #endif /* CONFIG_CMD_PCI */
519 #ifdef CONFIG_SERIAL_TAG
521 * called when setting up ATAGS before booting kernel
522 * populate serialnum from the following (in order of priority):
526 void get_board_serial(struct tag_serialnr *serialnr)
528 char *serial = getenv("serial#");
532 serialnr->low = simple_strtoul(serial, NULL, 10);
533 } else if (ventana_info.model[0]) {
535 serialnr->low = ventana_info.serial;
547 int board_early_init_f(void)
551 #if defined(CONFIG_VIDEO_IPUV3)
559 gd->ram_size = imx_ddr_size();
565 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
567 clrsetbits_le32(&iomuxc_regs->gpr[1],
568 IOMUXC_GPR1_OTG_ID_MASK,
569 IOMUXC_GPR1_OTG_ID_GPIO1);
571 /* address of linux boot parameters */
572 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
574 #ifdef CONFIG_CMD_NAND
577 #ifdef CONFIG_MXC_SPI
582 #ifdef CONFIG_CMD_SATA
585 /* read Gateworks EEPROM into global struct (used later) */
586 board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
588 setup_iomux_gpio(board_type, &ventana_info);
593 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
595 * called during late init (after relocation and after board_init())
596 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
601 struct ventana_board_info *info = &ventana_info;
602 unsigned char buf[4];
604 int quiet; /* Quiet or minimal output mode */
609 quiet = simple_strtol(p, NULL, 10);
611 setenv("quiet", "0");
613 puts("\nGateworks Corporation Copyright 2014\n");
614 if (info->model[0]) {
615 printf("Model: %s\n", info->model);
616 printf("MFGDate: %02x-%02x-%02x%02x\n",
617 info->mfgdate[0], info->mfgdate[1],
618 info->mfgdate[2], info->mfgdate[3]);
619 printf("Serial:%d\n", info->serial);
621 puts("Invalid EEPROM - board will not function fully\n");
626 /* Display GSC firmware revision/CRC/status */
630 if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
632 buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
639 #ifdef CONFIG_CMD_BMODE
641 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
642 * see Table 8-11 and Table 5-9
643 * BOOT_CFG1[7] = 1 (boot from NAND)
644 * BOOT_CFG1[5] = 0 - raw NAND
645 * BOOT_CFG1[4] = 0 - default pad settings
646 * BOOT_CFG1[3:2] = 00 - devices = 1
647 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
648 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
649 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
650 * BOOT_CFG2[0] = 0 - Reset time 12ms
652 static const struct boot_mode board_boot_modes[] = {
653 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
654 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
660 int misc_init_r(void)
662 struct ventana_board_info *info = &ventana_info;
664 /* set env vars based on EEPROM data */
665 if (ventana_info.model[0]) {
666 char str[16], fdt[36];
668 const char *cputype = "";
672 * FDT name will be prefixed with CPU type. Three versions
673 * will be created each increasingly generic and bootloader
674 * env scripts will try loading each from most specific to
677 if (is_cpu_type(MXC_CPU_MX6Q) ||
678 is_cpu_type(MXC_CPU_MX6D))
680 else if (is_cpu_type(MXC_CPU_MX6DL) ||
681 is_cpu_type(MXC_CPU_MX6SOLO))
683 setenv("soctype", cputype);
684 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
685 setenv("flash_layout", "large");
687 setenv("flash_layout", "normal");
688 memset(str, 0, sizeof(str));
689 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
690 str[i] = tolower(info->model[i]);
691 setenv("model", str);
692 if (!getenv("fdt_file")) {
693 sprintf(fdt, "%s-%s.dtb", cputype, str);
694 setenv("fdt_file", fdt);
696 p = strchr(str, '-');
700 setenv("model_base", str);
701 sprintf(fdt, "%s-%s.dtb", cputype, str);
702 setenv("fdt_file1", fdt);
703 if (board_type != GW551x &&
704 board_type != GW552x &&
705 board_type != GW553x)
709 sprintf(fdt, "%s-%s.dtb", cputype, str);
710 setenv("fdt_file2", fdt);
713 /* initialize env from EEPROM */
714 if (test_bit(EECONFIG_ETH0, info->config) &&
715 !getenv("ethaddr")) {
716 eth_setenv_enetaddr("ethaddr", info->mac0);
718 if (test_bit(EECONFIG_ETH1, info->config) &&
719 !getenv("eth1addr")) {
720 eth_setenv_enetaddr("eth1addr", info->mac1);
723 /* board serial-number */
724 sprintf(str, "%6d", info->serial);
725 setenv("serial#", str);
728 sprintf(str, "%d", (int) (gd->ram_size >> 20));
729 setenv("mem_mb", str);
733 /* setup baseboard specific GPIO based on board and env */
734 setup_board_gpio(board_type, info);
736 #ifdef CONFIG_CMD_BMODE
737 add_board_boot_modes(board_boot_modes);
740 /* disable boot watchdog */
741 gsc_boot_wd_disable();
746 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
748 static int ft_sethdmiinfmt(void *blob, char *mode)
755 off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
759 if (0 == strcasecmp(mode, "yuv422bt656")) {
760 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
763 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
764 fdt_setprop_u32(blob, off, "vidout_trc", 1);
765 fdt_setprop_u32(blob, off, "vidout_blc", 1);
766 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
767 printf(" set HDMI input mode to %s\n", mode);
768 } else if (0 == strcasecmp(mode, "yuv422smp")) {
769 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
772 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
773 fdt_setprop_u32(blob, off, "vidout_trc", 0);
774 fdt_setprop_u32(blob, off, "vidout_blc", 0);
775 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
776 printf(" set HDMI input mode to %s\n", mode);
784 /* enable a property of a node if the node is found */
785 static inline void ft_enable_path(void *blob, const char *path)
787 int i = fdt_path_offset(blob, path);
789 debug("enabling %s\n", path);
790 fdt_status_okay(blob, i);
794 /* remove a property of a node if the node is found */
795 static inline void ft_delprop_path(void *blob, const char *path,
798 int i = fdt_path_offset(blob, path);
800 debug("removing %s/%s\n", path, name);
801 fdt_delprop(blob, i, name);
806 * called prior to booting kernel or by 'fdt boardsetup' command
808 * unless 'fdt_noauto' env var is set we will update the following in the DTB:
809 * - mtd partitions based on mtdparts/mtdids env
810 * - system-serial (board serial num from EEPROM)
811 * - board (full model from EEPROM)
812 * - peripherals removed from DTB if not loaded on board (per EEPROM config)
814 int ft_board_setup(void *blob, bd_t *bd)
816 struct ventana_board_info *info = &ventana_info;
817 struct ventana_eeprom_config *cfg;
818 struct node_info nodes[] = {
819 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
820 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
822 const char *model = getenv("model");
823 const char *display = getenv("display");
827 /* determine board revision */
828 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
829 if (ventana_info.model[i] >= 'A') {
830 rev = ventana_info.model[i];
835 if (getenv("fdt_noauto")) {
836 puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
840 if (test_bit(EECONFIG_NAND, info->config)) {
841 /* Update partition nodes using info from mtdparts env var */
842 puts(" Updating MTD partitions...\n");
843 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
846 /* Update display timings from display env var */
848 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
850 printf(" Set display timings for %s...\n", display);
853 printf(" Adjusting FDT per EEPROM for %s...\n", model);
855 /* board serial number */
856 fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
857 strlen(getenv("serial#")) + 1);
859 /* board (model contains model from device-tree) */
860 fdt_setprop(blob, 0, "board", info->model,
861 strlen((const char *)info->model) + 1);
863 /* set desired digital video capture format */
864 ft_sethdmiinfmt(blob, getenv("hdmiinfmt"));
867 * disable serial2 node for GW54xx for compatibility with older
868 * 3.10.x kernel that improperly had this node enabled in the DT
870 if (board_type == GW54xx) {
871 i = fdt_path_offset(blob,
872 "/soc/aips-bus@02100000/serial@021ec000");
874 fdt_del_node(blob, i);
878 * disable wdog1/wdog2 nodes for GW51xx below revC to work around
879 * errata causing wdog timer to be unreliable.
881 if (board_type == GW51xx && rev >= 'A' && rev < 'C') {
882 i = fdt_path_offset(blob,
883 "/soc/aips-bus@02000000/wdog@020bc000");
885 fdt_status_disabled(blob, i);
888 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
889 else if (board_type == GW52xx && info->model[4] == '2') {
893 i = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
895 range = (u32 *)fdt_getprop(blob, i, "reset-gpio",
899 i = fdt_path_offset(blob,
900 "/soc/aips-bus@02000000/gpio@020a4000");
902 handle = fdt_get_phandle(blob, i);
904 range[0] = cpu_to_fdt32(handle);
905 range[1] = cpu_to_fdt32(23);
909 /* these have broken usd_vsel */
910 if (strstr((const char *)info->model, "SP318-B") ||
911 strstr((const char *)info->model, "SP331-B"))
912 gpio_cfg[board_type].usd_vsel = 0;
916 * isolate CSI0_DATA_EN for GW551x below revB to work around
917 * errata causing non functional digital video in (it is not hooked up)
919 else if (board_type == GW551x && rev == 'A') {
922 const u32 *handle = NULL;
924 i = fdt_node_offset_by_compatible(blob, -1,
925 "fsl,imx-tda1997x-video");
927 handle = fdt_getprop(blob, i, "pinctrl-0", NULL);
929 i = fdt_node_offset_by_phandle(blob,
930 fdt32_to_cpu(*handle));
932 range = (u32 *)fdt_getprop(blob, i, "fsl,pins", &len);
935 for (i = 0; i < len; i += 6) {
936 u32 mux_reg = fdt32_to_cpu(range[i+0]);
937 u32 conf_reg = fdt32_to_cpu(range[i+1]);
938 /* mux PAD_CSI0_DATA_EN to GPIO */
939 if (is_cpu_type(MXC_CPU_MX6Q) &&
940 mux_reg == 0x260 && conf_reg == 0x630)
941 range[i+3] = cpu_to_fdt32(0x5);
942 else if (!is_cpu_type(MXC_CPU_MX6Q) &&
943 mux_reg == 0x08c && conf_reg == 0x3a0)
944 range[i+3] = cpu_to_fdt32(0x5);
946 fdt_setprop_inplace(blob, i, "fsl,pins", range, len);
949 /* set BT656 video format */
950 ft_sethdmiinfmt(blob, "yuv422bt656");
954 for (i = 0; i < gpio_cfg[board_type].num_gpios; i++) {
955 struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
958 sprintf(arg, "dio%d", i);
961 if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
964 sprintf(path, "/soc/aips-bus@02000000/pwm@%08x",
965 0x02080000 + (0x4000 * (cfg->pwm_param - 1)));
966 printf(" Enabling pwm%d for DIO%d\n",
968 ft_enable_path(blob, path);
972 /* remove no-1-8-v if UHS-I support is present */
973 if (gpio_cfg[board_type].usd_vsel) {
974 debug("Enabling UHS-I support\n");
975 ft_delprop_path(blob, "/soc/aips-bus@02100000/usdhc@02198000",
981 * remove nodes by alias path if EEPROM config tells us the
982 * peripheral is not loaded on the board.
984 if (getenv("fdt_noconfig")) {
985 puts(" Skiping periperhal config (fdt_noconfig defined)\n");
990 if (!test_bit(cfg->bit, info->config)) {
991 fdt_del_node_and_alias(blob, cfg->dtalias ?
992 cfg->dtalias : cfg->name);
999 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
1001 static struct mxc_serial_platdata ventana_mxc_serial_plat = {
1002 .reg = (struct mxc_uart *)UART2_BASE,
1005 U_BOOT_DEVICE(ventana_serial) = {
1006 .name = "serial_mxc",
1007 .platdata = &ventana_mxc_serial_plat,