2 * Copyright (C) 2013 Gateworks Corporation
4 * Author: Tim Harvey <tharvey@gateworks.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clock.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/iomux.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/mxc_hdmi.h>
16 #include <asm/arch/crm_regs.h>
17 #include <asm/arch/sys_proto.h>
19 #include <asm/imx-common/iomux-v3.h>
20 #include <asm/imx-common/mxc_i2c.h>
21 #include <asm/imx-common/boot_mode.h>
22 #include <asm/imx-common/sata.h>
23 #include <asm/imx-common/video.h>
24 #include <jffs2/load_kernel.h>
27 #include <linux/ctype.h>
28 #include <fdt_support.h>
29 #include <fsl_esdhc.h>
35 #include <power/pmic.h>
36 #include <power/ltc3676_pmic.h>
37 #include <power/pfuze100_pmic.h>
38 #include <fdt_support.h>
39 #include <jffs2/load_kernel.h>
40 #include <spi_flash.h>
43 #include "ventana_eeprom.h"
45 DECLARE_GLOBAL_DATA_PTR;
47 /* GPIO's common to all baseboards */
48 #define GP_PHY_RST IMX_GPIO_NR(1, 30)
49 #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
50 #define GP_SD3_CD IMX_GPIO_NR(7, 0)
51 #define GP_RS232_EN IMX_GPIO_NR(2, 11)
52 #define GP_MSATA_SEL IMX_GPIO_NR(2, 8)
54 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
55 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
56 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
58 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
59 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
60 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
62 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
63 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
64 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
66 #define SPI_PAD_CTRL (PAD_CTL_HYS | \
67 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
68 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
70 #define DIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
71 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
72 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
74 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
75 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
76 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
78 #define IRQ_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
79 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
80 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
82 #define DIO_PAD_CFG (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION)
86 * EEPROM board info struct populated by read_eeprom so that we only have to
89 struct ventana_board_info ventana_info;
93 /* UART1: Function varies per baseboard */
94 iomux_v3_cfg_t const uart1_pads[] = {
95 IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
96 IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
99 /* UART2: Serial Console */
100 iomux_v3_cfg_t const uart2_pads[] = {
101 IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
102 IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
105 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
108 struct i2c_pads_info mx6q_i2c_pad_info0 = {
110 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
111 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
112 .gp = IMX_GPIO_NR(3, 21)
115 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
116 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
117 .gp = IMX_GPIO_NR(3, 28)
120 struct i2c_pads_info mx6dl_i2c_pad_info0 = {
122 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
123 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
124 .gp = IMX_GPIO_NR(3, 21)
127 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
128 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
129 .gp = IMX_GPIO_NR(3, 28)
133 /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
134 struct i2c_pads_info mx6q_i2c_pad_info1 = {
136 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
137 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
138 .gp = IMX_GPIO_NR(4, 12)
141 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
142 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
143 .gp = IMX_GPIO_NR(4, 13)
146 struct i2c_pads_info mx6dl_i2c_pad_info1 = {
148 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
149 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
150 .gp = IMX_GPIO_NR(4, 12)
153 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
154 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
155 .gp = IMX_GPIO_NR(4, 13)
159 /* I2C3: Misc/Expansion */
160 struct i2c_pads_info mx6q_i2c_pad_info2 = {
162 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
163 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
164 .gp = IMX_GPIO_NR(1, 3)
167 .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
168 .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
169 .gp = IMX_GPIO_NR(1, 6)
172 struct i2c_pads_info mx6dl_i2c_pad_info2 = {
174 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
175 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
176 .gp = IMX_GPIO_NR(1, 3)
179 .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
180 .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
181 .gp = IMX_GPIO_NR(1, 6)
186 iomux_v3_cfg_t const usdhc3_pads[] = {
187 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
188 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
189 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
190 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
191 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
192 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
194 IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
198 iomux_v3_cfg_t const enet_pads[] = {
199 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
200 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
201 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
202 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
203 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
204 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
205 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
206 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
207 MUX_PAD_CTRL(ENET_PAD_CTRL)),
208 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
209 MUX_PAD_CTRL(ENET_PAD_CTRL)),
210 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
211 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
212 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
213 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
214 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
215 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
216 MUX_PAD_CTRL(ENET_PAD_CTRL)),
218 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
222 iomux_v3_cfg_t const nfc_pads[] = {
223 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
224 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
225 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
226 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
227 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
228 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
229 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
230 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
231 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
232 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
233 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
234 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
235 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
236 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
237 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
240 #ifdef CONFIG_CMD_NAND
241 static void setup_gpmi_nand(void)
243 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
245 /* config gpmi nand iomux */
246 SETUP_IOMUX_PADS(nfc_pads);
248 /* config gpmi and bch clock to 100 MHz */
249 clrsetbits_le32(&mxc_ccm->cs2cdr,
250 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
251 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
252 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
253 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
254 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
255 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
257 /* enable gpmi and bch clock gating */
258 setbits_le32(&mxc_ccm->CCGR4,
259 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
260 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
261 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
262 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
263 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
265 /* enable apbh clock gating */
266 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
270 static void setup_iomux_enet(void)
272 SETUP_IOMUX_PADS(enet_pads);
274 /* toggle PHY_RST# */
275 gpio_direction_output(GP_PHY_RST, 0);
277 gpio_set_value(GP_PHY_RST, 1);
280 static void setup_iomux_uart(void)
282 SETUP_IOMUX_PADS(uart1_pads);
283 SETUP_IOMUX_PADS(uart2_pads);
286 #ifdef CONFIG_USB_EHCI_MX6
287 iomux_v3_cfg_t const usb_pads[] = {
288 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
289 IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
291 IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
294 int board_ehci_hcd_init(int port)
296 struct ventana_board_info *info = &ventana_info;
298 SETUP_IOMUX_PADS(usb_pads);
300 /* Reset USB HUB (present on GW54xx/GW53xx) */
301 switch (info->model[3]) {
302 case '3': /* GW53xx */
303 case '5': /* GW552x */
304 SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG);
305 gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
307 gpio_set_value(IMX_GPIO_NR(1, 9), 1);
309 case '4': /* GW54xx */
310 SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG);
311 gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
313 gpio_set_value(IMX_GPIO_NR(1, 16), 1);
320 int board_ehci_power(int port, int on)
324 gpio_set_value(GP_USB_OTG_PWR, on);
327 #endif /* CONFIG_USB_EHCI_MX6 */
329 #ifdef CONFIG_FSL_ESDHC
330 struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
332 int board_mmc_getcd(struct mmc *mmc)
335 gpio_direction_input(GP_SD3_CD);
336 return !gpio_get_value(GP_SD3_CD);
339 int board_mmc_init(bd_t *bis)
341 /* Only one USDHC controller on Ventana */
342 SETUP_IOMUX_PADS(usdhc3_pads);
343 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
344 usdhc_cfg.max_bus_width = 4;
346 return fsl_esdhc_initialize(bis, &usdhc_cfg);
348 #endif /* CONFIG_FSL_ESDHC */
350 #ifdef CONFIG_MXC_SPI
351 iomux_v3_cfg_t const ecspi1_pads[] = {
353 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
354 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
355 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
356 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
359 int board_spi_cs_gpio(unsigned bus, unsigned cs)
361 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
364 static void setup_spi(void)
366 gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
367 SETUP_IOMUX_PADS(ecspi1_pads);
371 /* configure eth0 PHY board-specific LED behavior */
372 int board_phy_config(struct phy_device *phydev)
377 if (phydev->phy_id == 0x1410dd1) {
379 * Page 3, Register 16: LED[2:0] Function Control Register
380 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
381 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
383 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
384 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
387 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
388 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
391 if (phydev->drv->config)
392 phydev->drv->config(phydev);
397 int board_eth_init(bd_t *bis)
401 #ifdef CONFIG_FEC_MXC
402 if (board_type != GW552x)
407 /* For otg ethernet*/
408 usb_eth_initialize(bis);
414 #if defined(CONFIG_VIDEO_IPUV3)
416 static void enable_hdmi(struct display_info_t const *dev)
418 imx_enable_hdmi_phy();
421 static int detect_i2c(struct display_info_t const *dev)
423 return i2c_set_bus_num(dev->bus) == 0 &&
424 i2c_probe(dev->addr) == 0;
427 static void enable_lvds(struct display_info_t const *dev)
429 struct iomuxc *iomux = (struct iomuxc *)
432 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
433 u32 reg = readl(&iomux->gpr[2]);
434 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
435 writel(reg, &iomux->gpr[2]);
437 /* Enable Backlight */
438 SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
439 gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
442 struct display_info_t const displays[] = {{
446 .pixfmt = IPU_PIX_FMT_RGB24,
447 .detect = detect_hdmi,
448 .enable = enable_hdmi,
462 .vmode = FB_VMODE_NONINTERLACED
464 /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
467 .pixfmt = IPU_PIX_FMT_LVDS666,
468 .detect = detect_i2c,
469 .enable = enable_lvds,
471 .name = "Hannstar-XGA",
483 .vmode = FB_VMODE_NONINTERLACED
485 size_t display_count = ARRAY_SIZE(displays);
487 static void setup_display(void)
489 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
490 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
495 /* Turn on LDB0,IPU,IPU DI0 clocks */
496 reg = __raw_readl(&mxc_ccm->CCGR3);
497 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
498 writel(reg, &mxc_ccm->CCGR3);
500 /* set LDB0, LDB1 clk select to 011/011 */
501 reg = readl(&mxc_ccm->cs2cdr);
502 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
503 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
504 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
505 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
506 writel(reg, &mxc_ccm->cs2cdr);
508 reg = readl(&mxc_ccm->cscmr2);
509 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
510 writel(reg, &mxc_ccm->cscmr2);
512 reg = readl(&mxc_ccm->chsccdr);
513 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
514 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
515 writel(reg, &mxc_ccm->chsccdr);
517 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
518 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
519 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
520 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
521 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
522 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
523 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
524 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
525 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
526 writel(reg, &iomux->gpr[2]);
528 reg = readl(&iomux->gpr[3]);
529 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
530 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
531 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
532 writel(reg, &iomux->gpr[3]);
534 /* Backlight CABEN on LVDS connector */
535 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
536 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
538 #endif /* CONFIG_VIDEO_IPUV3 */
541 * Baseboard specific GPIO
544 /* common to add baseboards */
545 static iomux_v3_cfg_t const gw_gpio_pads[] = {
547 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
549 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
553 static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
555 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
557 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
559 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
561 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
563 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
565 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
567 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
569 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
571 IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
573 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
576 static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
578 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
580 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
582 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
584 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
587 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
589 IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
591 IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
593 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
596 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
598 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
600 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
602 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
604 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
607 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
609 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
611 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
613 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
615 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
617 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
620 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
622 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
624 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
626 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
628 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
630 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
632 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
634 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
636 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
638 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
640 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
643 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
645 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
647 IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
649 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
651 IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG),
653 IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG),
655 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
657 IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
659 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
661 IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
663 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
665 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
667 IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
670 static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
672 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
674 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
676 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
678 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
680 IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG),
681 IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
682 IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG),
683 IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG),
684 IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG),
685 IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG),
687 IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
689 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
691 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
695 * each baseboard has 4 user configurable Digital IO lines which can
696 * be pinmuxed as a GPIO or in some cases a PWM
699 iomux_v3_cfg_t gpio_padmux[2];
701 iomux_v3_cfg_t pwm_padmux[2];
707 iomux_v3_cfg_t const *gpio_pads;
710 struct dio_cfg dio_cfg[4];
711 /* various gpios (0 if non-existent) */
725 struct ventana gpio_cfg[] = {
728 .gpio_pads = gw54xx_gpio_pads,
729 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
732 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
734 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
738 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
740 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
744 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
746 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
750 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
752 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
761 .pcie_rst = IMX_GPIO_NR(1, 29),
762 .mezz_pwren = IMX_GPIO_NR(4, 7),
763 .mezz_irq = IMX_GPIO_NR(4, 9),
764 .rs485en = IMX_GPIO_NR(3, 24),
765 .dioi2c_en = IMX_GPIO_NR(4, 5),
766 .pcie_sson = IMX_GPIO_NR(1, 20),
771 .gpio_pads = gw51xx_gpio_pads,
772 .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
775 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
781 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
783 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
787 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
789 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
793 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
795 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
803 .pcie_rst = IMX_GPIO_NR(1, 0),
804 .mezz_pwren = IMX_GPIO_NR(2, 19),
805 .mezz_irq = IMX_GPIO_NR(2, 18),
806 .gps_shdn = IMX_GPIO_NR(1, 2),
807 .vidin_en = IMX_GPIO_NR(5, 20),
808 .wdis = IMX_GPIO_NR(7, 12),
813 .gpio_pads = gw52xx_gpio_pads,
814 .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
817 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
823 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
825 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
829 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
831 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
835 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
846 .pcie_rst = IMX_GPIO_NR(1, 29),
847 .mezz_pwren = IMX_GPIO_NR(2, 19),
848 .mezz_irq = IMX_GPIO_NR(2, 18),
849 .gps_shdn = IMX_GPIO_NR(1, 27),
850 .vidin_en = IMX_GPIO_NR(3, 31),
851 .usb_sel = IMX_GPIO_NR(1, 2),
852 .wdis = IMX_GPIO_NR(7, 12),
857 .gpio_pads = gw53xx_gpio_pads,
858 .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
861 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
867 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
869 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
873 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
875 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
879 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
890 .pcie_rst = IMX_GPIO_NR(1, 29),
891 .mezz_pwren = IMX_GPIO_NR(2, 19),
892 .mezz_irq = IMX_GPIO_NR(2, 18),
893 .gps_shdn = IMX_GPIO_NR(1, 27),
894 .vidin_en = IMX_GPIO_NR(3, 31),
895 .wdis = IMX_GPIO_NR(7, 12),
900 .gpio_pads = gw54xx_gpio_pads,
901 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
904 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
906 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
910 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
912 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
916 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
918 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
922 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
924 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
933 .pcie_rst = IMX_GPIO_NR(1, 29),
934 .mezz_pwren = IMX_GPIO_NR(2, 19),
935 .mezz_irq = IMX_GPIO_NR(2, 18),
936 .rs485en = IMX_GPIO_NR(7, 1),
937 .vidin_en = IMX_GPIO_NR(3, 31),
938 .dioi2c_en = IMX_GPIO_NR(4, 5),
939 .pcie_sson = IMX_GPIO_NR(1, 20),
940 .wdis = IMX_GPIO_NR(5, 17),
945 .gpio_pads = gw552x_gpio_pads,
946 .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
949 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
955 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
957 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
961 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
963 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
967 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
978 .pcie_rst = IMX_GPIO_NR(1, 29),
982 /* setup board specific PMIC */
983 int power_init_board(void)
988 /* configure PFUZE100 PMIC */
989 if (board_type == GW54xx || board_type == GW54proto) {
990 power_pfuze100_init(CONFIG_I2C_PMIC);
991 p = pmic_get("PFUZE100");
992 if (p && !pmic_probe(p)) {
993 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
994 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
996 /* Set VGEN1 to 1.5V and enable */
997 pmic_reg_read(p, PFUZE100_VGEN1VOL, ®);
998 reg &= ~(LDO_VOL_MASK);
999 reg |= (LDOA_1_50V | LDO_EN);
1000 pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
1002 /* Set SWBST to 5.0V and enable */
1003 pmic_reg_read(p, PFUZE100_SWBSTCON1, ®);
1004 reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
1005 reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
1006 pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
1010 /* configure LTC3676 PMIC */
1012 power_ltc3676_init(CONFIG_I2C_PMIC);
1013 p = pmic_get("LTC3676_PMIC");
1014 if (p && !pmic_probe(p)) {
1015 puts("PMIC: LTC3676\n");
1016 /* set board-specific scalar to 1225mV for IMX6Q@1GHz */
1017 if (is_cpu_type(MXC_CPU_MX6Q)) {
1018 /* mask PGOOD during SW1 transition */
1019 reg = 0x1d | LTC3676_PGOOD_MASK;
1020 pmic_reg_write(p, LTC3676_DVB1B, reg);
1021 /* set SW1 (VDD_SOC) to 1259mV */
1023 pmic_reg_write(p, LTC3676_DVB1A, reg);
1025 /* mask PGOOD during SW3 transition */
1026 reg = 0x1d | LTC3676_PGOOD_MASK;
1027 pmic_reg_write(p, LTC3676_DVB3B, reg);
1028 /*set SW3 (VDD_ARM) to 1259mV */
1030 pmic_reg_write(p, LTC3676_DVB3A, reg);
1038 /* setup GPIO pinmux and default configuration per baseboard */
1039 static void setup_board_gpio(int board)
1041 struct ventana_board_info *info = &ventana_info;
1046 int quiet = simple_strtol(getenv("quiet"), NULL, 10);
1048 if (board >= GW_UNKNOWN)
1052 gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
1055 if (is_cpu_type(MXC_CPU_MX6Q) &&
1056 test_bit(EECONFIG_SATA, info->config)) {
1057 gpio_direction_output(GP_MSATA_SEL,
1058 (hwconfig("msata")) ? 1 : 0);
1060 gpio_direction_output(GP_MSATA_SEL, 0);
1063 #if !defined(CONFIG_CMD_PCI)
1064 /* assert PCI_RST# (released by OS when clock is valid) */
1065 gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
1068 /* turn off (active-high) user LED's */
1069 for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) {
1070 if (gpio_cfg[board].leds[i])
1071 gpio_direction_output(gpio_cfg[board].leds[i], 1);
1074 /* Expansion Mezzanine IO */
1075 if (gpio_cfg[board].mezz_pwren)
1076 gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
1077 if (gpio_cfg[board].mezz_irq)
1078 gpio_direction_input(gpio_cfg[board].mezz_irq);
1080 /* RS485 Transmit Enable */
1081 if (gpio_cfg[board].rs485en)
1082 gpio_direction_output(gpio_cfg[board].rs485en, 0);
1085 if (gpio_cfg[board].gps_shdn)
1086 gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
1088 /* Analog video codec power enable */
1089 if (gpio_cfg[board].vidin_en)
1090 gpio_direction_output(gpio_cfg[board].vidin_en, 1);
1093 if (gpio_cfg[board].dioi2c_en)
1094 gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
1096 /* PCICK_SSON: disable spread-spectrum clock */
1097 if (gpio_cfg[board].pcie_sson)
1098 gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
1100 /* USBOTG Select (PCISKT or FrontPanel) */
1101 if (gpio_cfg[board].usb_sel)
1102 gpio_direction_output(gpio_cfg[board].usb_sel, 0);
1104 /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
1105 if (gpio_cfg[board].wdis)
1106 gpio_direction_output(gpio_cfg[board].wdis, 1);
1109 * Configure DIO pinmux/padctl registers
1110 * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
1112 for (i = 0; i < 4; i++) {
1113 struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
1114 iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
1115 unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
1117 sprintf(arg, "dio%d", i);
1120 s = hwconfig_subarg(arg, "padctrl", &len);
1122 ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16)
1123 & 0x1ffff) | MUX_MODE_SION;
1125 if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
1127 printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i,
1128 (cfg->gpio_param/32)+1,
1132 imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
1134 gpio_direction_input(cfg->gpio_param);
1135 } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
1138 printf("DIO%d: pwm%d\n", i, cfg->pwm_param);
1139 imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
1140 MUX_PAD_CTRL(ctrl));
1145 if (is_cpu_type(MXC_CPU_MX6Q) &&
1146 (test_bit(EECONFIG_SATA, info->config))) {
1147 printf("MSATA: %s\n", (hwconfig("msata") ?
1148 "enabled" : "disabled"));
1150 printf("RS232: %s\n", (hwconfig("rs232")) ?
1151 "enabled" : "disabled");
1155 #if defined(CONFIG_CMD_PCI)
1156 int imx6_pcie_toggle_reset(void)
1158 if (board_type < GW_UNKNOWN) {
1159 uint pin = gpio_cfg[board_type].pcie_rst;
1160 gpio_direction_output(pin, 0);
1162 gpio_direction_output(pin, 1);
1168 * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
1169 * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
1170 * properly and assert reset for 100ms.
1172 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
1173 unsigned short vendor, unsigned short device,
1174 unsigned short class)
1178 debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
1179 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
1180 if (vendor == PCI_VENDOR_ID_PLX &&
1181 (device & 0xfff0) == 0x8600 &&
1182 PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
1183 debug("configuring PLX 860X downstream PERST#\n");
1184 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
1185 dw |= 0xaaa8; /* GPIO1-7 outputs */
1186 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
1188 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
1189 dw |= 0xfe; /* GPIO1-7 output high */
1190 pci_hose_write_config_dword(hose, dev, 0x644, dw);
1195 #endif /* CONFIG_CMD_PCI */
1197 #ifdef CONFIG_SERIAL_TAG
1199 * called when setting up ATAGS before booting kernel
1200 * populate serialnum from the following (in order of priority):
1204 void get_board_serial(struct tag_serialnr *serialnr)
1206 char *serial = getenv("serial#");
1210 serialnr->low = simple_strtoul(serial, NULL, 10);
1211 } else if (ventana_info.model[0]) {
1213 serialnr->low = ventana_info.serial;
1225 /* called from SPL board_init_f() */
1226 int board_early_init_f(void)
1229 gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
1231 #if defined(CONFIG_VIDEO_IPUV3)
1239 gd->ram_size = imx_ddr_size();
1243 int board_init(void)
1245 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
1247 clrsetbits_le32(&iomuxc_regs->gpr[1],
1248 IOMUXC_GPR1_OTG_ID_MASK,
1249 IOMUXC_GPR1_OTG_ID_GPIO1);
1251 /* address of linux boot parameters */
1252 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
1254 #ifdef CONFIG_CMD_NAND
1257 #ifdef CONFIG_MXC_SPI
1260 if (is_cpu_type(MXC_CPU_MX6Q)) {
1261 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
1262 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
1263 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
1265 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
1266 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
1267 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
1270 #ifdef CONFIG_CMD_SATA
1273 /* read Gateworks EEPROM into global struct (used later) */
1274 board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
1276 /* board-specifc GPIO iomux */
1277 SETUP_IOMUX_PADS(gw_gpio_pads);
1278 if (board_type < GW_UNKNOWN) {
1279 iomux_v3_cfg_t const *p = gpio_cfg[board_type].gpio_pads;
1280 int count = gpio_cfg[board_type].num_pads;
1282 imx_iomux_v3_setup_multiple_pads(p, count);
1288 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
1290 * called during late init (after relocation and after board_init())
1291 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
1294 int checkboard(void)
1296 struct ventana_board_info *info = &ventana_info;
1297 unsigned char buf[4];
1299 int quiet; /* Quiet or minimal output mode */
1302 p = getenv("quiet");
1304 quiet = simple_strtol(p, NULL, 10);
1306 setenv("quiet", "0");
1308 puts("\nGateworks Corporation Copyright 2014\n");
1309 if (info->model[0]) {
1310 printf("Model: %s\n", info->model);
1311 printf("MFGDate: %02x-%02x-%02x%02x\n",
1312 info->mfgdate[0], info->mfgdate[1],
1313 info->mfgdate[2], info->mfgdate[3]);
1314 printf("Serial:%d\n", info->serial);
1316 puts("Invalid EEPROM - board will not function fully\n");
1321 /* Display GSC firmware revision/CRC/status */
1322 i2c_set_bus_num(CONFIG_I2C_GSC);
1323 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) {
1324 printf("GSC: v%d", buf[0]);
1325 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) {
1326 printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */
1327 printf(" 0x%02x", buf[0]); /* irq status */
1332 if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
1334 buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
1341 #ifdef CONFIG_CMD_BMODE
1343 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
1344 * see Table 8-11 and Table 5-9
1345 * BOOT_CFG1[7] = 1 (boot from NAND)
1346 * BOOT_CFG1[5] = 0 - raw NAND
1347 * BOOT_CFG1[4] = 0 - default pad settings
1348 * BOOT_CFG1[3:2] = 00 - devices = 1
1349 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
1350 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
1351 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
1352 * BOOT_CFG2[0] = 0 - Reset time 12ms
1354 static const struct boot_mode board_boot_modes[] = {
1355 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
1356 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
1362 int misc_init_r(void)
1364 struct ventana_board_info *info = &ventana_info;
1367 /* set env vars based on EEPROM data */
1368 if (ventana_info.model[0]) {
1369 char str[16], fdt[36];
1371 const char *cputype = "";
1375 * FDT name will be prefixed with CPU type. Three versions
1376 * will be created each increasingly generic and bootloader
1377 * env scripts will try loading each from most specific to
1380 if (is_cpu_type(MXC_CPU_MX6Q) ||
1381 is_cpu_type(MXC_CPU_MX6D))
1383 else if (is_cpu_type(MXC_CPU_MX6DL) ||
1384 is_cpu_type(MXC_CPU_MX6SOLO))
1386 setenv("soctype", cputype);
1387 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
1388 setenv("flash_layout", "large");
1390 setenv("flash_layout", "normal");
1391 memset(str, 0, sizeof(str));
1392 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
1393 str[i] = tolower(info->model[i]);
1394 if (!getenv("model"))
1395 setenv("model", str);
1396 if (!getenv("fdt_file")) {
1397 sprintf(fdt, "%s-%s.dtb", cputype, str);
1398 setenv("fdt_file", fdt);
1400 p = strchr(str, '-');
1404 setenv("model_base", str);
1405 if (!getenv("fdt_file1")) {
1406 sprintf(fdt, "%s-%s.dtb", cputype, str);
1407 setenv("fdt_file1", fdt);
1409 if (board_type != GW552x)
1413 if (!getenv("fdt_file2")) {
1414 sprintf(fdt, "%s-%s.dtb", cputype, str);
1415 setenv("fdt_file2", fdt);
1419 /* initialize env from EEPROM */
1420 if (test_bit(EECONFIG_ETH0, info->config) &&
1421 !getenv("ethaddr")) {
1422 eth_setenv_enetaddr("ethaddr", info->mac0);
1424 if (test_bit(EECONFIG_ETH1, info->config) &&
1425 !getenv("eth1addr")) {
1426 eth_setenv_enetaddr("eth1addr", info->mac1);
1429 /* board serial-number */
1430 sprintf(str, "%6d", info->serial);
1431 setenv("serial#", str);
1435 /* setup baseboard specific GPIO pinmux and config */
1436 setup_board_gpio(board_type);
1438 #ifdef CONFIG_CMD_BMODE
1439 add_board_boot_modes(board_boot_modes);
1443 * The Gateworks System Controller implements a boot
1444 * watchdog (always enabled) as a workaround for IMX6 boot related
1446 * ERR005768 - no fix scheduled
1447 * ERR006282 - fixed in silicon r1.2
1448 * ERR007117 - fixed in silicon r1.3
1449 * ERR007220 - fixed in silicon r1.3
1450 * ERR007926 - no fix scheduled
1451 * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
1453 * Disable the boot watchdog and display/clear the timeout flag if set
1455 i2c_set_bus_num(CONFIG_I2C_GSC);
1456 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) {
1457 reg |= (1 << GSC_SC_CTRL1_WDDIS);
1458 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
1459 puts("Error: could not disable GSC Watchdog\n");
1461 puts("Error: could not disable GSC Watchdog\n");
1463 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1)) {
1464 if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */
1465 puts("GSC boot watchdog timeout detected\n");
1466 reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */
1467 gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1);
1474 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1477 * called prior to booting kernel or by 'fdt boardsetup' command
1479 * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1480 * - mtd partitions based on mtdparts/mtdids env
1481 * - system-serial (board serial num from EEPROM)
1482 * - board (full model from EEPROM)
1483 * - peripherals removed from DTB if not loaded on board (per EEPROM config)
1485 void ft_board_setup(void *blob, bd_t *bd)
1487 struct ventana_board_info *info = &ventana_info;
1488 struct ventana_eeprom_config *cfg;
1489 struct node_info nodes[] = {
1490 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
1491 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
1493 const char *model = getenv("model");
1495 if (getenv("fdt_noauto")) {
1496 puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
1500 /* Update partition nodes using info from mtdparts env var */
1501 puts(" Updating MTD partitions...\n");
1502 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1505 puts("invalid board info: Leaving FDT fully enabled\n");
1508 printf(" Adjusting FDT per EEPROM for %s...\n", model);
1510 /* board serial number */
1511 fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
1512 strlen(getenv("serial#")) + 1);
1514 /* board (model contains model from device-tree) */
1515 fdt_setprop(blob, 0, "board", info->model,
1516 strlen((const char *)info->model) + 1);
1519 * Peripheral Config:
1520 * remove nodes by alias path if EEPROM config tells us the
1521 * peripheral is not loaded on the board.
1523 if (getenv("fdt_noconfig")) {
1524 puts(" Skiping periperhal config (fdt_noconfig defined)\n");
1529 if (!test_bit(cfg->bit, info->config)) {
1530 fdt_del_node_and_alias(blob, cfg->dtalias ?
1531 cfg->dtalias : cfg->name);
1536 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */