board/gateworks/gw_ventana/gw_ventana.c

   1 /*
   2  * Copyright (C) 2013 Gateworks Corporation
   3  *
   4  * Author: Tim Harvey <tharvey@gateworks.com>
   5  *
   6  * SPDX-License-Identifier: GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/mxc_hdmi.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/gpio.h>
  19 #include <asm/imx-common/iomux-v3.h>
  20 #include <asm/imx-common/mxc_i2c.h>
  21 #include <asm/imx-common/boot_mode.h>
  22 #include <asm/imx-common/sata.h>
  23 #include <asm/imx-common/video.h>
  24 #include <jffs2/load_kernel.h>
  25 #include <hwconfig.h>
  26 #include <i2c.h>
  27 #include <linux/ctype.h>
  28 #include <fdt_support.h>
  29 #include <fsl_esdhc.h>
  30 #include <miiphy.h>
  31 #include <mmc.h>
  32 #include <mtd_node.h>
  33 #include <netdev.h>
  34 #include <power/pmic.h>
  35 #include <power/ltc3676_pmic.h>
  36 #include <power/pfuze100_pmic.h>
  37 #include <fdt_support.h>
  38 #include <jffs2/load_kernel.h>
  39 #include <spi_flash.h>
  40
  41 #include "gsc.h"
  42 #include "ventana_eeprom.h"
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 /* GPIO's common to all baseboards */
  47 #define GP_PHY_RST      IMX_GPIO_NR(1, 30)
  48 #define GP_USB_OTG_PWR  IMX_GPIO_NR(3, 22)
  49 #define GP_SD3_CD       IMX_GPIO_NR(7, 0)
  50 #define GP_RS232_EN     IMX_GPIO_NR(2, 11)
  51 #define GP_MSATA_SEL    IMX_GPIO_NR(2, 8)
  52
  53 /* I2C bus numbers */
  54 #define I2C_GSC         0
  55 #define I2C_PMIC        1
  56
  57 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  58         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  59         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  60
  61 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  62         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
  63         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  64
  65 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  66         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  67         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  68
  69 #define SPI_PAD_CTRL (PAD_CTL_HYS |                             \
  70         PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
  71         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  72
  73 #define DIO_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |              \
  74         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  75         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  76
  77 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  78         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  79         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  80
  81 /*
  82  * EEPROM board info struct populated by read_eeprom so that we only have to
  83  * read it once.
  84  */
  85 static struct ventana_board_info ventana_info;
  86
  87 int board_type;
  88
  89 /* UART1: Function varies per baseboard */
  90 iomux_v3_cfg_t const uart1_pads[] = {
  91         MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  92         MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  93 };
  94
  95 /* UART2: Serial Console */
  96 iomux_v3_cfg_t const uart2_pads[] = {
  97         MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  98         MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  99 };
 100
 101 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 102
 103 /* I2C1: GSC */
 104 struct i2c_pads_info i2c_pad_info0 = {
 105         .scl = {
 106                 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
 107                 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
 108                 .gp = IMX_GPIO_NR(3, 21)
 109         },
 110         .sda = {
 111                 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
 112                 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
 113                 .gp = IMX_GPIO_NR(3, 28)
 114         }
 115 };
 116
 117 /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
 118 struct i2c_pads_info i2c_pad_info1 = {
 119         .scl = {
 120                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
 121                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
 122                 .gp = IMX_GPIO_NR(4, 12)
 123         },
 124         .sda = {
 125                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 126                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 127                 .gp = IMX_GPIO_NR(4, 13)
 128         }
 129 };
 130
 131 /* I2C3: Misc/Expansion */
 132 struct i2c_pads_info i2c_pad_info2 = {
 133         .scl = {
 134                 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
 135                 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
 136                 .gp = IMX_GPIO_NR(1, 3)
 137         },
 138         .sda = {
 139                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
 140                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
 141                 .gp = IMX_GPIO_NR(1, 6)
 142         }
 143 };
 144
 145 /* MMC */
 146 iomux_v3_cfg_t const usdhc3_pads[] = {
 147         MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 148         MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 149         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 150         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 151         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 152         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 153         MX6_PAD_SD3_DAT5__GPIO7_IO00  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 154 };
 155
 156 /* ENET */
 157 iomux_v3_cfg_t const enet_pads[] = {
 158         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 159         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 160         MX6_PAD_RGMII_TXC__RGMII_TXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 161         MX6_PAD_RGMII_TD0__RGMII_TD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 162         MX6_PAD_RGMII_TD1__RGMII_TD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 163         MX6_PAD_RGMII_TD2__RGMII_TD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 164         MX6_PAD_RGMII_TD3__RGMII_TD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 165         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 166         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 167         MX6_PAD_RGMII_RXC__RGMII_RXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 168         MX6_PAD_RGMII_RD0__RGMII_RD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 169         MX6_PAD_RGMII_RD1__RGMII_RD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 170         MX6_PAD_RGMII_RD2__RGMII_RD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 171         MX6_PAD_RGMII_RD3__RGMII_RD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 172         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 173         /* PHY nRST */
 174         MX6_PAD_ENET_TXD0__GPIO1_IO30           | MUX_PAD_CTRL(NO_PAD_CTRL),
 175 };
 176
 177 /* NAND */
 178 iomux_v3_cfg_t const nfc_pads[] = {
 179         MX6_PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL),
 180         MX6_PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL),
 181         MX6_PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL),
 182         MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
 183         MX6_PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL),
 184         MX6_PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL),
 185         MX6_PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL),
 186         MX6_PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL),
 187         MX6_PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL),
 188         MX6_PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL),
 189         MX6_PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL),
 190         MX6_PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL),
 191         MX6_PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL),
 192         MX6_PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL),
 193         MX6_PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL),
 194 };
 195
 196 #ifdef CONFIG_CMD_NAND
 197 static void setup_gpmi_nand(void)
 198 {
 199         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 200
 201         /* config gpmi nand iomux */
 202         imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
 203
 204         /* config gpmi and bch clock to 100 MHz */
 205         clrsetbits_le32(&mxc_ccm->cs2cdr,
 206                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 207                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 208                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 209                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 210                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 211                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 212
 213         /* enable gpmi and bch clock gating */
 214         setbits_le32(&mxc_ccm->CCGR4,
 215                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 216                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 217                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 218                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 219                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 220
 221         /* enable apbh clock gating */
 222         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 223 }
 224 #endif
 225
 226 static void setup_iomux_enet(void)
 227 {
 228         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 229
 230         /* toggle PHY_RST# */
 231         gpio_direction_output(GP_PHY_RST, 0);
 232         mdelay(2);
 233         gpio_set_value(GP_PHY_RST, 1);
 234 }
 235
 236 static void setup_iomux_uart(void)
 237 {
 238         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 239         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 240 }
 241
 242 #ifdef CONFIG_USB_EHCI_MX6
 243 iomux_v3_cfg_t const usb_pads[] = {
 244         MX6_PAD_GPIO_1__USB_OTG_ID   | MUX_PAD_CTRL(DIO_PAD_CTRL),
 245         MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(DIO_PAD_CTRL),
 246         MX6_PAD_EIM_D22__GPIO3_IO22  | MUX_PAD_CTRL(DIO_PAD_CTRL), /* OTG PWR */
 247 };
 248
 249 int board_ehci_hcd_init(int port)
 250 {
 251         struct ventana_board_info *info = &ventana_info;
 252
 253         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 254
 255         /* Reset USB HUB (present on GW54xx/GW53xx) */
 256         switch (info->model[3]) {
 257         case '3': /* GW53xx */
 258                 imx_iomux_v3_setup_pad(MX6_PAD_GPIO_9__GPIO1_IO09|
 259                                        MUX_PAD_CTRL(NO_PAD_CTRL));
 260                 gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
 261                 mdelay(2);
 262                 gpio_set_value(IMX_GPIO_NR(1, 9), 1);
 263                 break;
 264         case '4': /* GW54xx */
 265                 imx_iomux_v3_setup_pad(MX6_PAD_SD1_DAT0__GPIO1_IO16 |
 266                                        MUX_PAD_CTRL(NO_PAD_CTRL));
 267                 gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
 268                 mdelay(2);
 269                 gpio_set_value(IMX_GPIO_NR(1, 16), 1);
 270                 break;
 271         }
 272
 273         return 0;
 274 }
 275
 276 int board_ehci_power(int port, int on)
 277 {
 278         if (port)
 279                 return 0;
 280         gpio_set_value(GP_USB_OTG_PWR, on);
 281         return 0;
 282 }
 283 #endif /* CONFIG_USB_EHCI_MX6 */
 284
 285 #ifdef CONFIG_FSL_ESDHC
 286 struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
 287
 288 int board_mmc_getcd(struct mmc *mmc)
 289 {
 290         /* Card Detect */
 291         gpio_direction_input(GP_SD3_CD);
 292         return !gpio_get_value(GP_SD3_CD);
 293 }
 294
 295 int board_mmc_init(bd_t *bis)
 296 {
 297         /* Only one USDHC controller on Ventana */
 298         imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 299         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 300         usdhc_cfg.max_bus_width = 4;
 301
 302         return fsl_esdhc_initialize(bis, &usdhc_cfg);
 303 }
 304 #endif /* CONFIG_FSL_ESDHC */
 305
 306 #ifdef CONFIG_MXC_SPI
 307 iomux_v3_cfg_t const ecspi1_pads[] = {
 308         /* SS1 */
 309         MX6_PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(SPI_PAD_CTRL),
 310         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 311         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 312         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 313 };
 314
 315 static void setup_spi(void)
 316 {
 317         gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
 318         imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
 319                                          ARRAY_SIZE(ecspi1_pads));
 320 }
 321 #endif
 322
 323 /* configure eth0 PHY board-specific LED behavior */
 324 int board_phy_config(struct phy_device *phydev)
 325 {
 326         unsigned short val;
 327
 328         /* Marvel 88E1510 */
 329         if (phydev->phy_id == 0x1410dd1) {
 330                 /*
 331                  * Page 3, Register 16: LED[2:0] Function Control Register
 332                  * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
 333                  * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
 334                  */
 335                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
 336                 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
 337                 val &= 0xff00;
 338                 val |= 0x0017;
 339                 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
 340                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 341         }
 342
 343         if (phydev->drv->config)
 344                 phydev->drv->config(phydev);
 345
 346         return 0;
 347 }
 348
 349 int board_eth_init(bd_t *bis)
 350 {
 351         setup_iomux_enet();
 352
 353 #ifdef CONFIG_FEC_MXC
 354         cpu_eth_init(bis);
 355 #endif
 356
 357 #ifdef CONFIG_CI_UDC
 358         /* For otg ethernet*/
 359         usb_eth_initialize(bis);
 360 #endif
 361
 362         return 0;
 363 }
 364
 365 #if defined(CONFIG_VIDEO_IPUV3)
 366
 367 static void enable_hdmi(struct display_info_t const *dev)
 368 {
 369         imx_enable_hdmi_phy();
 370 }
 371
 372 static int detect_i2c(struct display_info_t const *dev)
 373 {
 374         return i2c_set_bus_num(dev->bus) == 0 &&
 375                 i2c_probe(dev->addr) == 0;
 376 }
 377
 378 static void enable_lvds(struct display_info_t const *dev)
 379 {
 380         struct iomuxc *iomux = (struct iomuxc *)
 381                                 IOMUXC_BASE_ADDR;
 382
 383         /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
 384         u32 reg = readl(&iomux->gpr[2]);
 385         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 386         writel(reg, &iomux->gpr[2]);
 387
 388         /* Enable Backlight */
 389         imx_iomux_v3_setup_pad(MX6_PAD_SD1_CMD__GPIO1_IO18 |
 390                                MUX_PAD_CTRL(NO_PAD_CTRL));
 391         gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
 392 }
 393
 394 struct display_info_t const displays[] = {{
 395         /* HDMI Output */
 396         .bus    = -1,
 397         .addr   = 0,
 398         .pixfmt = IPU_PIX_FMT_RGB24,
 399         .detect = detect_hdmi,
 400         .enable = enable_hdmi,
 401         .mode   = {
 402                 .name           = "HDMI",
 403                 .refresh        = 60,
 404                 .xres           = 1024,
 405                 .yres           = 768,
 406                 .pixclock       = 15385,
 407                 .left_margin    = 220,
 408                 .right_margin   = 40,
 409                 .upper_margin   = 21,
 410                 .lower_margin   = 7,
 411                 .hsync_len      = 60,
 412                 .vsync_len      = 10,
 413                 .sync           = FB_SYNC_EXT,
 414                 .vmode          = FB_VMODE_NONINTERLACED
 415 } }, {
 416         /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
 417         .bus    = 2,
 418         .addr   = 0x4,
 419         .pixfmt = IPU_PIX_FMT_LVDS666,
 420         .detect = detect_i2c,
 421         .enable = enable_lvds,
 422         .mode   = {
 423                 .name           = "Hannstar-XGA",
 424                 .refresh        = 60,
 425                 .xres           = 1024,
 426                 .yres           = 768,
 427                 .pixclock       = 15385,
 428                 .left_margin    = 220,
 429                 .right_margin   = 40,
 430                 .upper_margin   = 21,
 431                 .lower_margin   = 7,
 432                 .hsync_len      = 60,
 433                 .vsync_len      = 10,
 434                 .sync           = FB_SYNC_EXT,
 435                 .vmode          = FB_VMODE_NONINTERLACED
 436 } } };
 437 size_t display_count = ARRAY_SIZE(displays);
 438
 439 static void setup_display(void)
 440 {
 441         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 442         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 443         int reg;
 444
 445         enable_ipu_clock();
 446         imx_setup_hdmi();
 447         /* Turn on LDB0,IPU,IPU DI0 clocks */
 448         reg = __raw_readl(&mxc_ccm->CCGR3);
 449         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 450         writel(reg, &mxc_ccm->CCGR3);
 451
 452         /* set LDB0, LDB1 clk select to 011/011 */
 453         reg = readl(&mxc_ccm->cs2cdr);
 454         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 455                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 456         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 457               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 458         writel(reg, &mxc_ccm->cs2cdr);
 459
 460         reg = readl(&mxc_ccm->cscmr2);
 461         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 462         writel(reg, &mxc_ccm->cscmr2);
 463
 464         reg = readl(&mxc_ccm->chsccdr);
 465         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 466                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 467         writel(reg, &mxc_ccm->chsccdr);
 468
 469         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 470              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 471              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 472              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 473              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 474              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 475              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 476              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 477              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 478         writel(reg, &iomux->gpr[2]);
 479
 480         reg = readl(&iomux->gpr[3]);
 481         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 482             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 483                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 484         writel(reg, &iomux->gpr[3]);
 485
 486         /* Backlight CABEN on LVDS connector */
 487         imx_iomux_v3_setup_pad(MX6_PAD_SD2_CLK__GPIO1_IO10 |
 488                                MUX_PAD_CTRL(NO_PAD_CTRL));
 489         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 490 }
 491 #endif /* CONFIG_VIDEO_IPUV3 */
 492
 493 /*
 494  * Baseboard specific GPIO
 495  */
 496
 497 /* common to add baseboards */
 498 static iomux_v3_cfg_t const gw_gpio_pads[] = {
 499         /* MSATA_EN */
 500         MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
 501         /* RS232_EN# */
 502         MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
 503 };
 504
 505 /* prototype */
 506 static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
 507         /* PANLEDG# */
 508         MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
 509         /* PANLEDR# */
 510         MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
 511         /* LOCLED# */
 512         MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 513         /* RS485_EN */
 514         MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL),
 515         /* IOEXP_PWREN# */
 516         MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
 517         /* IOEXP_IRQ# */
 518         MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 519         /* VID_EN */
 520         MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
 521         /* DIOI2C_DIS# */
 522         MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 523         /* PCICK_SSON */
 524         MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
 525         /* PCI_RST# */
 526         MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 527 };
 528
 529 static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
 530         /* PANLEDG# */
 531         MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
 532         /* PANLEDR# */
 533         MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
 534         /* IOEXP_PWREN# */
 535         MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
 536         /* IOEXP_IRQ# */
 537         MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 538
 539         /* GPS_SHDN */
 540         MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
 541         /* VID_PWR */
 542         MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
 543         /* PCI_RST# */
 544         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 545 };
 546
 547 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
 548         /* PANLEDG# */
 549         MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
 550         /* PANLEDR# */
 551         MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
 552         /* IOEXP_PWREN# */
 553         MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
 554         /* IOEXP_IRQ# */
 555         MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 556
 557         /* MX6_LOCLED# */
 558         MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 559         /* GPS_SHDN */
 560         MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
 561         /* USBOTG_SEL */
 562         MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
 563         /* VID_PWR */
 564         MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
 565         /* PCI_RST# */
 566         MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 567 };
 568
 569 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
 570         /* PANLEDG# */
 571         MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
 572         /* PANLEDR# */
 573         MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
 574         /* IOEXP_PWREN# */
 575         MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
 576         /* IOEXP_IRQ# */
 577         MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 578
 579         /* MX6_LOCLED# */
 580         MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 581         /* GPS_SHDN */
 582         MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
 583         /* VID_EN */
 584         MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
 585         /* PCI_RST# */
 586         MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 587 };
 588
 589 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
 590         /* PANLEDG# */
 591         MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
 592         /* PANLEDR# */
 593         MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 594         /* MX6_LOCLED# */
 595         MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 596         /* MIPI_DIO */
 597         MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 598         /* RS485_EN */
 599         MX6_PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
 600         /* IOEXP_PWREN# */
 601         MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
 602         /* IOEXP_IRQ# */
 603         MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
 604         /* DIOI2C_DIS# */
 605         MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 606         /* DIOI2C_DIS# */
 607         MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 608         /* PCICK_SSON */
 609         MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
 610         /* PCI_RST# */
 611         MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 612 };
 613
 614 /*
 615  * each baseboard has 4 user configurable Digital IO lines which can
 616  * be pinmuxed as a GPIO or in some cases a PWM
 617  */
 618 struct dio_cfg {
 619         iomux_v3_cfg_t gpio_padmux;
 620         unsigned gpio_param;
 621         iomux_v3_cfg_t pwm_padmux;
 622         unsigned pwm_param;
 623 };
 624
 625 struct ventana {
 626         /* pinmux */
 627         iomux_v3_cfg_t const *gpio_pads;
 628         int num_pads;
 629         /* DIO pinmux/val */
 630         struct dio_cfg dio_cfg[4];
 631         /* various gpios (0 if non-existent) */
 632         int leds[3];
 633         int pcie_rst;
 634         int mezz_pwren;
 635         int mezz_irq;
 636         int rs485en;
 637         int gps_shdn;
 638         int vidin_en;
 639         int dioi2c_en;
 640         int pcie_sson;
 641         int usb_sel;
 642 };
 643
 644 struct ventana gpio_cfg[] = {
 645         /* GW5400proto */
 646         {
 647                 .gpio_pads = gw54xx_gpio_pads,
 648                 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads),
 649                 .dio_cfg = {
 650                         { MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9),
 651                           MX6_PAD_GPIO_9__PWM1_OUT, 1 },
 652                         { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
 653                           MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
 654                         { MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9),
 655                           MX6_PAD_SD4_DAT1__PWM3_OUT, 3 },
 656                         { MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10),
 657                           MX6_PAD_SD4_DAT2__PWM4_OUT, 4 },
 658                 },
 659                 .leds = {
 660                         IMX_GPIO_NR(4, 6),
 661                         IMX_GPIO_NR(4, 10),
 662                         IMX_GPIO_NR(4, 15),
 663                 },
 664                 .pcie_rst = IMX_GPIO_NR(1, 29),
 665                 .mezz_pwren = IMX_GPIO_NR(4, 7),
 666                 .mezz_irq = IMX_GPIO_NR(4, 9),
 667                 .rs485en = IMX_GPIO_NR(3, 24),
 668                 .dioi2c_en = IMX_GPIO_NR(4,  5),
 669                 .pcie_sson = IMX_GPIO_NR(1, 20),
 670         },
 671
 672         /* GW51xx */
 673         {
 674                 .gpio_pads = gw51xx_gpio_pads,
 675                 .num_pads = ARRAY_SIZE(gw51xx_gpio_pads),
 676                 .dio_cfg = {
 677                         { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
 678                           0, 0 },
 679                         { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
 680                           MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
 681                         { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
 682                           MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
 683                         { MX6_PAD_SD1_CMD__GPIO1_IO18, IMX_GPIO_NR(1, 18),
 684                           MX6_PAD_SD1_CMD__PWM4_OUT, 4 },
 685                 },
 686                 .leds = {
 687                         IMX_GPIO_NR(4, 6),
 688                         IMX_GPIO_NR(4, 10),
 689                 },
 690                 .pcie_rst = IMX_GPIO_NR(1, 0),
 691                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 692                 .mezz_irq = IMX_GPIO_NR(2, 18),
 693                 .gps_shdn = IMX_GPIO_NR(1, 2),
 694                 .vidin_en = IMX_GPIO_NR(5, 20),
 695         },
 696
 697         /* GW52xx */
 698         {
 699                 .gpio_pads = gw52xx_gpio_pads,
 700                 .num_pads = ARRAY_SIZE(gw52xx_gpio_pads),
 701                 .dio_cfg = {
 702                         { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
 703                           0, 0 },
 704                         { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
 705                           MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
 706                         { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
 707                           MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
 708                         { MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20),
 709                           0, 0 },
 710                 },
 711                 .leds = {
 712                         IMX_GPIO_NR(4, 6),
 713                         IMX_GPIO_NR(4, 7),
 714                         IMX_GPIO_NR(4, 15),
 715                 },
 716                 .pcie_rst = IMX_GPIO_NR(1, 29),
 717                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 718                 .mezz_irq = IMX_GPIO_NR(2, 18),
 719                 .gps_shdn = IMX_GPIO_NR(1, 27),
 720                 .vidin_en = IMX_GPIO_NR(3, 31),
 721                 .usb_sel = IMX_GPIO_NR(1, 2),
 722         },
 723
 724         /* GW53xx */
 725         {
 726                 .gpio_pads = gw53xx_gpio_pads,
 727                 .num_pads = ARRAY_SIZE(gw53xx_gpio_pads),
 728                 .dio_cfg = {
 729                         { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
 730                           0, 0 },
 731                         { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
 732                           MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
 733                         { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
 734                           MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
 735                         { MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20),
 736                           0, 0 },
 737                 },
 738                 .leds = {
 739                         IMX_GPIO_NR(4, 6),
 740                         IMX_GPIO_NR(4, 7),
 741                         IMX_GPIO_NR(4, 15),
 742                 },
 743                 .pcie_rst = IMX_GPIO_NR(1, 29),
 744                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 745                 .mezz_irq = IMX_GPIO_NR(2, 18),
 746                 .gps_shdn = IMX_GPIO_NR(1, 27),
 747                 .vidin_en = IMX_GPIO_NR(3, 31),
 748         },
 749
 750         /* GW54xx */
 751         {
 752                 .gpio_pads = gw54xx_gpio_pads,
 753                 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads),
 754                 .dio_cfg = {
 755                         { MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9),
 756                           MX6_PAD_GPIO_9__PWM1_OUT, 1 },
 757                         { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
 758                           MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
 759                         { MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9),
 760                           MX6_PAD_SD4_DAT1__PWM3_OUT, 3 },
 761                         { MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10),
 762                           MX6_PAD_SD4_DAT2__PWM4_OUT, 4 },
 763                 },
 764                 .leds = {
 765                         IMX_GPIO_NR(4, 6),
 766                         IMX_GPIO_NR(4, 7),
 767                         IMX_GPIO_NR(4, 15),
 768                 },
 769                 .pcie_rst = IMX_GPIO_NR(1, 29),
 770                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 771                 .mezz_irq = IMX_GPIO_NR(2, 18),
 772                 .rs485en = IMX_GPIO_NR(7, 1),
 773                 .vidin_en = IMX_GPIO_NR(3, 31),
 774                 .dioi2c_en = IMX_GPIO_NR(4,  5),
 775                 .pcie_sson = IMX_GPIO_NR(1, 20),
 776         },
 777 };
 778
 779 /* setup board specific PMIC */
 780 int power_init_board(void)
 781 {
 782         struct pmic *p;
 783         u32 reg;
 784
 785         /* configure PFUZE100 PMIC */
 786         if (board_type == GW54xx || board_type == GW54proto) {
 787                 power_pfuze100_init(I2C_PMIC);
 788                 p = pmic_get("PFUZE100_PMIC");
 789                 if (p && !pmic_probe(p)) {
 790                         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 791                         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 792
 793                         /* Set VGEN1 to 1.5V and enable */
 794                         pmic_reg_read(p, PFUZE100_VGEN1VOL, &reg);
 795                         reg &= ~(LDO_VOL_MASK);
 796                         reg |= (LDOA_1_50V | LDO_EN);
 797                         pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
 798
 799                         /* Set SWBST to 5.0V and enable */
 800                         pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
 801                         reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
 802                         reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
 803                         pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
 804                 }
 805         }
 806
 807         /* configure LTC3676 PMIC */
 808         else {
 809                 power_ltc3676_init(I2C_PMIC);
 810                 p = pmic_get("LTC3676_PMIC");
 811                 if (p && !pmic_probe(p)) {
 812                         puts("PMIC:  LTC3676\n");
 813                         /* set board-specific scalar to 1225mV for IMX6Q@1GHz */
 814                         if (is_cpu_type(MXC_CPU_MX6Q)) {
 815                                 /* mask PGOOD during SW1 transition */
 816                                 reg = 0x1d | LTC3676_PGOOD_MASK;
 817                                 pmic_reg_write(p, LTC3676_DVB1B, reg);
 818                                 /* set SW1 (VDD_SOC) to 1259mV */
 819                                 reg = 0x1d;
 820                                 pmic_reg_write(p, LTC3676_DVB1A, reg);
 821
 822                                 /* mask PGOOD during SW3 transition */
 823                                 reg = 0x1d | LTC3676_PGOOD_MASK;
 824                                 pmic_reg_write(p, LTC3676_DVB3B, reg);
 825                                 /*set SW3 (VDD_ARM) to 1259mV */
 826                                 reg = 0x1d;
 827                                 pmic_reg_write(p, LTC3676_DVB3A, reg);
 828                         }
 829                 }
 830         }
 831
 832         return 0;
 833 }
 834
 835 /* setup GPIO pinmux and default configuration per baseboard */
 836 static void setup_board_gpio(int board)
 837 {
 838         struct ventana_board_info *info = &ventana_info;
 839         const char *s;
 840         char arg[10];
 841         size_t len;
 842         int i;
 843         int quiet = simple_strtol(getenv("quiet"), NULL, 10);
 844
 845         if (board >= GW_UNKNOWN)
 846                 return;
 847
 848         /* RS232_EN# */
 849         gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
 850
 851         /* MSATA Enable */
 852         if (is_cpu_type(MXC_CPU_MX6Q) &&
 853             test_bit(EECONFIG_SATA, info->config)) {
 854                 gpio_direction_output(GP_MSATA_SEL,
 855                                       (hwconfig("msata")) ?  1 : 0);
 856         } else {
 857                 gpio_direction_output(GP_MSATA_SEL, 0);
 858         }
 859
 860         /*
 861          * assert PCI_RST# (released by OS when clock is valid)
 862          * TODO: figure out why leaving this de-asserted from PCI scan on boot
 863          *       causes linux pcie driver to hang during enumeration
 864          */
 865         gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
 866
 867         /* turn off (active-high) user LED's */
 868         for (i = 0; i < 4; i++) {
 869                 if (gpio_cfg[board].leds[i])
 870                         gpio_direction_output(gpio_cfg[board].leds[i], 1);
 871         }
 872
 873         /* Expansion Mezzanine IO */
 874         gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
 875         gpio_direction_input(gpio_cfg[board].mezz_irq);
 876
 877         /* RS485 Transmit Enable */
 878         if (gpio_cfg[board].rs485en)
 879                 gpio_direction_output(gpio_cfg[board].rs485en, 0);
 880
 881         /* GPS_SHDN */
 882         if (gpio_cfg[board].gps_shdn)
 883                 gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
 884
 885         /* Analog video codec power enable */
 886         if (gpio_cfg[board].vidin_en)
 887                 gpio_direction_output(gpio_cfg[board].vidin_en, 1);
 888
 889         /* DIOI2C_DIS# */
 890         if (gpio_cfg[board].dioi2c_en)
 891                 gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
 892
 893         /* PCICK_SSON: disable spread-spectrum clock */
 894         if (gpio_cfg[board].pcie_sson)
 895                 gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
 896
 897         /* USBOTG Select (PCISKT or FrontPanel) */
 898         if (gpio_cfg[board].usb_sel)
 899                 gpio_direction_output(gpio_cfg[board].usb_sel, 0);
 900
 901         /*
 902          * Configure DIO pinmux/padctl registers
 903          * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
 904          */
 905         for (i = 0; i < 4; i++) {
 906                 struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
 907                 unsigned ctrl = DIO_PAD_CTRL;
 908
 909                 sprintf(arg, "dio%d", i);
 910                 if (!hwconfig(arg))
 911                         continue;
 912                 s = hwconfig_subarg(arg, "padctrl", &len);
 913                 if (s)
 914                         ctrl = simple_strtoul(s, NULL, 16) & 0x3ffff;
 915                 if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
 916                         if (!quiet) {
 917                                 printf("DIO%d:  GPIO%d_IO%02d (gpio-%d)\n", i,
 918                                        (cfg->gpio_param/32)+1,
 919                                        cfg->gpio_param%32,
 920                                        cfg->gpio_param);
 921                         }
 922                         imx_iomux_v3_setup_pad(cfg->gpio_padmux |
 923                                                MUX_PAD_CTRL(ctrl));
 924                         gpio_direction_input(cfg->gpio_param);
 925                 } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
 926                            cfg->pwm_padmux) {
 927                         if (!quiet)
 928                                 printf("DIO%d:  pwm%d\n", i, cfg->pwm_param);
 929                         imx_iomux_v3_setup_pad(cfg->pwm_padmux |
 930                                                MUX_PAD_CTRL(ctrl));
 931                 }
 932         }
 933
 934         if (!quiet) {
 935                 if (is_cpu_type(MXC_CPU_MX6Q) &&
 936                     (test_bit(EECONFIG_SATA, info->config))) {
 937                         printf("MSATA: %s\n", (hwconfig("msata") ?
 938                                "enabled" : "disabled"));
 939                 }
 940                 printf("RS232: %s\n", (hwconfig("rs232")) ?
 941                        "enabled" : "disabled");
 942         }
 943 }
 944
 945 #if defined(CONFIG_CMD_PCI)
 946 int imx6_pcie_toggle_reset(void)
 947 {
 948         if (board_type < GW_UNKNOWN) {
 949                 gpio_direction_output(gpio_cfg[board_type].pcie_rst, 0);
 950                 mdelay(50);
 951                 gpio_direction_output(gpio_cfg[board_type].pcie_rst, 1);
 952         }
 953         return 0;
 954 }
 955 #endif /* CONFIG_CMD_PCI */
 956
 957 #ifdef CONFIG_SERIAL_TAG
 958 /*
 959  * called when setting up ATAGS before booting kernel
 960  * populate serialnum from the following (in order of priority):
 961  *   serial# env var
 962  *   eeprom
 963  */
 964 void get_board_serial(struct tag_serialnr *serialnr)
 965 {
 966         char *serial = getenv("serial#");
 967
 968         if (serial) {
 969                 serialnr->high = 0;
 970                 serialnr->low = simple_strtoul(serial, NULL, 10);
 971         } else if (ventana_info.model[0]) {
 972                 serialnr->high = 0;
 973                 serialnr->low = ventana_info.serial;
 974         } else {
 975                 serialnr->high = 0;
 976                 serialnr->low = 0;
 977         }
 978 }
 979 #endif
 980
 981 /*
 982  * Board Support
 983  */
 984
 985 int board_early_init_f(void)
 986 {
 987         setup_iomux_uart();
 988         gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
 989
 990 #if defined(CONFIG_VIDEO_IPUV3)
 991         setup_display();
 992 #endif
 993         return 0;
 994 }
 995
 996 int dram_init(void)
 997 {
 998         gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
 999                                     CONFIG_DDR_MB*1024*1024);
1000
1001         return 0;
1002 }
1003
1004 int board_init(void)
1005 {
1006         struct iomuxc_base_regs *const iomuxc_regs
1007                 = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
1008
1009         clrsetbits_le32(&iomuxc_regs->gpr[1],
1010                         IOMUXC_GPR1_OTG_ID_MASK,
1011                         IOMUXC_GPR1_OTG_ID_GPIO1);
1012
1013         /* address of linux boot parameters */
1014         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
1015
1016 #ifdef CONFIG_CMD_NAND
1017         setup_gpmi_nand();
1018 #endif
1019 #ifdef CONFIG_MXC_SPI
1020         setup_spi();
1021 #endif
1022         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
1023         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
1024         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
1025
1026 #ifdef CONFIG_CMD_SATA
1027         setup_sata();
1028 #endif
1029         /* read Gateworks EEPROM into global struct (used later) */
1030         board_type = read_eeprom(I2C_GSC, &ventana_info);
1031
1032         /* board-specifc GPIO iomux */
1033         if (board_type < GW_UNKNOWN) {
1034                 imx_iomux_v3_setup_multiple_pads(gw_gpio_pads,
1035                                                  ARRAY_SIZE(gw_gpio_pads));
1036                 imx_iomux_v3_setup_multiple_pads(gpio_cfg[board_type].gpio_pads,
1037                                                  gpio_cfg[board_type].num_pads);
1038         }
1039
1040         return 0;
1041 }
1042
1043 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
1044 /*
1045  * called during late init (after relocation and after board_init())
1046  * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
1047  * EEPROM read.
1048  */
1049 int checkboard(void)
1050 {
1051         struct ventana_board_info *info = &ventana_info;
1052         unsigned char buf[4];
1053         const char *p;
1054         int quiet; /* Quiet or minimal output mode */
1055
1056         quiet = 0;
1057         p = getenv("quiet");
1058         if (p)
1059                 quiet = simple_strtol(p, NULL, 10);
1060         else
1061                 setenv("quiet", "0");
1062
1063         puts("\nGateworks Corporation Copyright 2014\n");
1064         if (info->model[0]) {
1065                 printf("Model: %s\n", info->model);
1066                 printf("MFGDate: %02x-%02x-%02x%02x\n",
1067                        info->mfgdate[0], info->mfgdate[1],
1068                        info->mfgdate[2], info->mfgdate[3]);
1069                 printf("Serial:%d\n", info->serial);
1070         } else {
1071                 puts("Invalid EEPROM - board will not function fully\n");
1072         }
1073         if (quiet)
1074                 return 0;
1075
1076         /* Display GSC firmware revision/CRC/status */
1077         i2c_set_bus_num(I2C_GSC);
1078         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) {
1079                 printf("GSC:   v%d", buf[0]);
1080                 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) {
1081                         printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */
1082                         printf(" 0x%02x", buf[0]); /* irq status */
1083                 }
1084                 puts("\n");
1085         }
1086         /* Display RTC */
1087         if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
1088                 printf("RTC:   %d\n",
1089                        buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
1090         }
1091
1092         return 0;
1093 }
1094 #endif
1095
1096 #ifdef CONFIG_CMD_BMODE
1097 /*
1098  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
1099  * see Table 8-11 and Table 5-9
1100  *  BOOT_CFG1[7] = 1 (boot from NAND)
1101  *  BOOT_CFG1[5] = 0 - raw NAND
1102  *  BOOT_CFG1[4] = 0 - default pad settings
1103  *  BOOT_CFG1[3:2] = 00 - devices = 1
1104  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
1105  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
1106  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
1107  *  BOOT_CFG2[0] = 0 - Reset time 12ms
1108  */
1109 static const struct boot_mode board_boot_modes[] = {
1110         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
1111         { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
1112         { NULL, 0 },
1113 };
1114 #endif
1115
1116 /* late init */
1117 int misc_init_r(void)
1118 {
1119         struct ventana_board_info *info = &ventana_info;
1120         unsigned char reg;
1121
1122         /* set env vars based on EEPROM data */
1123         if (ventana_info.model[0]) {
1124                 char str[16], fdt[36];
1125                 char *p;
1126                 const char *cputype = "";
1127                 int i;
1128
1129                 /*
1130                  * FDT name will be prefixed with CPU type.  Three versions
1131                  * will be created each increasingly generic and bootloader
1132                  * env scripts will try loading each from most specific to
1133                  * least.
1134                  */
1135                 if (is_cpu_type(MXC_CPU_MX6Q))
1136                         cputype = "imx6q";
1137                 else if (is_cpu_type(MXC_CPU_MX6DL))
1138                         cputype = "imx6dl";
1139                 memset(str, 0, sizeof(str));
1140                 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
1141                         str[i] = tolower(info->model[i]);
1142                 if (!getenv("model"))
1143                         setenv("model", str);
1144                 if (!getenv("fdt_file")) {
1145                         sprintf(fdt, "%s-%s.dtb", cputype, str);
1146                         setenv("fdt_file", fdt);
1147                 }
1148                 p = strchr(str, '-');
1149                 if (p) {
1150                         *p++ = 0;
1151
1152                         setenv("model_base", str);
1153                         if (!getenv("fdt_file1")) {
1154                                 sprintf(fdt, "%s-%s.dtb", cputype, str);
1155                                 setenv("fdt_file1", fdt);
1156                         }
1157                         str[4] = 'x';
1158                         str[5] = 'x';
1159                         str[6] = 0;
1160                         if (!getenv("fdt_file2")) {
1161                                 sprintf(fdt, "%s-%s.dtb", cputype, str);
1162                                 setenv("fdt_file2", fdt);
1163                         }
1164                 }
1165
1166                 /* initialize env from EEPROM */
1167                 if (test_bit(EECONFIG_ETH0, info->config) &&
1168                     !getenv("ethaddr")) {
1169                         eth_setenv_enetaddr("ethaddr", info->mac0);
1170                 }
1171                 if (test_bit(EECONFIG_ETH1, info->config) &&
1172                     !getenv("eth1addr")) {
1173                         eth_setenv_enetaddr("eth1addr", info->mac1);
1174                 }
1175
1176                 /* board serial-number */
1177                 sprintf(str, "%6d", info->serial);
1178                 setenv("serial#", str);
1179         }
1180
1181
1182         /* setup baseboard specific GPIO pinmux and config */
1183         setup_board_gpio(board_type);
1184
1185 #ifdef CONFIG_CMD_BMODE
1186         add_board_boot_modes(board_boot_modes);
1187 #endif
1188
1189         /*
1190          *  The Gateworks System Controller implements a boot
1191          *  watchdog (always enabled) as a workaround for IMX6 boot related
1192          *  errata such as:
1193          *    ERR005768 - no fix
1194          *    ERR006282 - fixed in silicon r1.3
1195          *    ERR007117 - fixed in silicon r1.3
1196          *    ERR007220 - fixed in silicon r1.3
1197          *  see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
1198          *
1199          * Disable the boot watchdog and display/clear the timeout flag if set
1200          */
1201         i2c_set_bus_num(I2C_GSC);
1202         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) {
1203                 reg |= (1 << GSC_SC_CTRL1_WDDIS);
1204                 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
1205                         puts("Error: could not disable GSC Watchdog\n");
1206         } else {
1207                 puts("Error: could not disable GSC Watchdog\n");
1208         }
1209         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1)) {
1210                 if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */
1211                         puts("GSC boot watchdog timeout detected");
1212                         reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */
1213                         gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1);
1214                 }
1215         }
1216
1217         return 0;
1218 }
1219
1220 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1221
1222 /* FDT aliases associated with EEPROM config bits */
1223 const char *fdt_aliases[] = {
1224         "ethernet0",
1225         "ethernet1",
1226         "hdmi_out",
1227         "ahci0",
1228         "pcie",
1229         "ssi0",
1230         "ssi1",
1231         "lcd0",
1232         "lvds0",
1233         "lvds1",
1234         "usb0",
1235         "usb1",
1236         "mmc0",
1237         "mmc1",
1238         "mmc2",
1239         "mmc3",
1240         "uart0",
1241         "uart1",
1242         "uart2",
1243         "uart3",
1244         "uart4",
1245         "ipu0",
1246         "ipu1",
1247         "can0",
1248         "mipi_dsi",
1249         "mipi_csi",
1250         "tzasc0",
1251         "tzasc1",
1252         "i2c0",
1253         "i2c1",
1254         "i2c2",
1255         "vpu",
1256         "csi0",
1257         "csi1",
1258         "caam",
1259         NULL,
1260         NULL,
1261         NULL,
1262         NULL,
1263         NULL,
1264         "spi0",
1265         "spi1",
1266         "spi2",
1267         "spi3",
1268         "spi4",
1269         "spi5",
1270         NULL,
1271         NULL,
1272         "pps",
1273         NULL,
1274         NULL,
1275         NULL,
1276         "hdmi_in",
1277         "cvbs_out",
1278         "cvbs_in",
1279         "nand",
1280         NULL,
1281         NULL,
1282         NULL,
1283         NULL,
1284         NULL,
1285         NULL,
1286         NULL,
1287         NULL,
1288 };
1289
1290 /*
1291  * called prior to booting kernel or by 'fdt boardsetup' command
1292  *
1293  * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1294  *  - mtd partitions based on mtdparts/mtdids env
1295  *  - system-serial (board serial num from EEPROM)
1296  *  - board (full model from EEPROM)
1297  *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
1298  */
1299 void ft_board_setup(void *blob, bd_t *bd)
1300 {
1301         int bit;
1302         struct ventana_board_info *info = &ventana_info;
1303         struct node_info nodes[] = {
1304                 { "sst,w25q256",          MTD_DEV_TYPE_NOR, },  /* SPI flash */
1305                 { "fsl,imx6q-gpmi-nand",  MTD_DEV_TYPE_NAND, }, /* NAND flash */
1306         };
1307         const char *model = getenv("model");
1308
1309         if (getenv("fdt_noauto")) {
1310                 puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
1311                 return;
1312         }
1313
1314         /* Update partition nodes using info from mtdparts env var */
1315         puts("   Updating MTD partitions...\n");
1316         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1317
1318         if (!model) {
1319                 puts("invalid board info: Leaving FDT fully enabled\n");
1320                 return;
1321         }
1322         printf("   Adjusting FDT per EEPROM for %s...\n", model);
1323
1324         /* board serial number */
1325         fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
1326                     strlen(getenv("serial#")) + 1);
1327
1328         /* board (model contains model from device-tree) */
1329         fdt_setprop(blob, 0, "board", info->model,
1330                     strlen((const char *)info->model) + 1);
1331
1332         /*
1333          * Peripheral Config:
1334          *  remove nodes by alias path if EEPROM config tells us the
1335          *  peripheral is not loaded on the board.
1336          */
1337         for (bit = 0; bit < 64; bit++) {
1338                 if (!test_bit(bit, info->config))
1339                         fdt_del_node_and_alias(blob, fdt_aliases[bit]);
1340         }
1341 }
1342 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
1343