2 * Copyright (C) 2013 Gateworks Corporation
4 * Author: Tim Harvey <tharvey@gateworks.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clock.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/iomux.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/crm_regs.h>
16 #include <asm/arch/sys_proto.h>
18 #include <asm/imx-common/iomux-v3.h>
19 #include <asm/imx-common/mxc_i2c.h>
20 #include <asm/imx-common/boot_mode.h>
21 #include <asm/imx-common/sata.h>
22 #include <jffs2/load_kernel.h>
25 #include <linux/ctype.h>
26 #include <fdt_support.h>
27 #include <fsl_esdhc.h>
32 #include <power/pmic.h>
33 #include <power/pfuze100_pmic.h>
34 #include <fdt_support.h>
35 #include <jffs2/load_kernel.h>
36 #include <spi_flash.h>
39 #include "ventana_eeprom.h"
41 DECLARE_GLOBAL_DATA_PTR;
43 /* GPIO's common to all baseboards */
44 #define GP_PHY_RST IMX_GPIO_NR(1, 30)
45 #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
46 #define GP_SD3_CD IMX_GPIO_NR(7, 0)
47 #define GP_RS232_EN IMX_GPIO_NR(2, 11)
48 #define GP_MSATA_SEL IMX_GPIO_NR(2, 8)
54 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
55 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
56 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
58 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
59 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
60 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
62 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
63 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
64 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
66 #define SPI_PAD_CTRL (PAD_CTL_HYS | \
67 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
68 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
70 #define DIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
71 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
72 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
74 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
75 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
76 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
79 * EEPROM board info struct populated by read_eeprom so that we only have to
82 static struct ventana_board_info ventana_info;
85 GW54proto, /* original GW5400-A prototype */
95 /* UART1: Function varies per baseboard */
96 iomux_v3_cfg_t const uart1_pads[] = {
97 MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
98 MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
101 /* UART2: Serial Console */
102 iomux_v3_cfg_t const uart2_pads[] = {
103 MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
104 MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
107 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
110 struct i2c_pads_info i2c_pad_info0 = {
112 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
113 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
114 .gp = IMX_GPIO_NR(3, 21)
117 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
118 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
119 .gp = IMX_GPIO_NR(3, 28)
123 /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
124 struct i2c_pads_info i2c_pad_info1 = {
126 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
127 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
128 .gp = IMX_GPIO_NR(4, 12)
131 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
132 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
133 .gp = IMX_GPIO_NR(4, 13)
137 /* I2C3: Misc/Expansion */
138 struct i2c_pads_info i2c_pad_info2 = {
140 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
141 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
142 .gp = IMX_GPIO_NR(1, 3)
145 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
146 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
147 .gp = IMX_GPIO_NR(1, 6)
152 iomux_v3_cfg_t const usdhc3_pads[] = {
153 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
154 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
155 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
156 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
157 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
158 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
159 MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
163 iomux_v3_cfg_t const enet_pads[] = {
164 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
165 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
166 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
167 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
168 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
169 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
170 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
171 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
172 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
173 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
174 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
175 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
176 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
177 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
178 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
180 MX6_PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
184 iomux_v3_cfg_t const nfc_pads[] = {
185 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
186 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
187 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
188 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
189 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
190 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
191 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
192 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
193 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
194 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
195 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
196 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
197 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
198 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
199 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
202 #ifdef CONFIG_CMD_NAND
203 static void setup_gpmi_nand(void)
205 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
207 /* config gpmi nand iomux */
208 imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
210 /* config gpmi and bch clock to 100 MHz */
211 clrsetbits_le32(&mxc_ccm->cs2cdr,
212 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
213 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
214 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
215 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
216 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
217 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
219 /* enable gpmi and bch clock gating */
220 setbits_le32(&mxc_ccm->CCGR4,
221 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
222 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
223 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
224 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
225 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
227 /* enable apbh clock gating */
228 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
232 static void setup_iomux_enet(void)
234 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
236 /* toggle PHY_RST# */
237 gpio_direction_output(GP_PHY_RST, 0);
239 gpio_set_value(GP_PHY_RST, 1);
242 static void setup_iomux_uart(void)
244 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
245 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
248 #ifdef CONFIG_USB_EHCI_MX6
249 iomux_v3_cfg_t const usb_pads[] = {
250 MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(DIO_PAD_CTRL),
251 MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(DIO_PAD_CTRL),
252 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(DIO_PAD_CTRL), /* OTG PWR */
255 int board_ehci_hcd_init(int port)
257 struct ventana_board_info *info = &ventana_info;
259 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
261 /* Reset USB HUB (present on GW54xx/GW53xx) */
262 switch (info->model[3]) {
263 case '3': /* GW53xx */
264 imx_iomux_v3_setup_pad(MX6_PAD_GPIO_9__GPIO1_IO09|
265 MUX_PAD_CTRL(NO_PAD_CTRL));
266 gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
268 gpio_set_value(IMX_GPIO_NR(1, 9), 1);
270 case '4': /* GW54xx */
271 imx_iomux_v3_setup_pad(MX6_PAD_SD1_DAT0__GPIO1_IO16 |
272 MUX_PAD_CTRL(NO_PAD_CTRL));
273 gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
275 gpio_set_value(IMX_GPIO_NR(1, 16), 1);
282 int board_ehci_power(int port, int on)
286 gpio_set_value(GP_USB_OTG_PWR, on);
289 #endif /* CONFIG_USB_EHCI_MX6 */
291 #ifdef CONFIG_FSL_ESDHC
292 struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
294 int board_mmc_getcd(struct mmc *mmc)
297 gpio_direction_input(GP_SD3_CD);
298 return !gpio_get_value(GP_SD3_CD);
301 int board_mmc_init(bd_t *bis)
303 /* Only one USDHC controller on Ventana */
304 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
305 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
306 usdhc_cfg.max_bus_width = 4;
308 return fsl_esdhc_initialize(bis, &usdhc_cfg);
310 #endif /* CONFIG_FSL_ESDHC */
312 #ifdef CONFIG_MXC_SPI
313 iomux_v3_cfg_t const ecspi1_pads[] = {
315 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
316 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
317 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
318 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
321 static void setup_spi(void)
323 gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
324 imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
325 ARRAY_SIZE(ecspi1_pads));
329 /* configure eth0 PHY board-specific LED behavior */
330 int board_phy_config(struct phy_device *phydev)
335 if (phydev->phy_id == 0x1410dd1) {
337 * Page 3, Register 16: LED[2:0] Function Control Register
338 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
339 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
341 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
342 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
345 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
346 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
349 if (phydev->drv->config)
350 phydev->drv->config(phydev);
355 int board_eth_init(bd_t *bis)
359 #ifdef CONFIG_FEC_MXC
364 /* For otg ethernet*/
365 usb_eth_initialize(bis);
371 /* read ventana EEPROM, check for validity, and return baseboard type */
379 struct ventana_board_info *info = &ventana_info;
380 unsigned char *buf = (unsigned char *)&ventana_info;
382 memset(info, 0, sizeof(ventana_info));
385 * On a board with a missing/depleted backup battery for GSC, the
386 * board may be ready to probe the GSC before its firmware is
387 * running. We will wait here indefinately for the GSC/EEPROM.
390 if (0 == i2c_set_bus_num(I2C_GSC) &&
391 0 == i2c_probe(GSC_EEPROM_ADDR))
396 /* read eeprom config section */
397 if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(ventana_info))) {
398 puts("EEPROM: Failed to read EEPROM\n");
404 if (info->model[0] != 'G' || info->model[1] != 'W') {
405 puts("EEPROM: Invalid Model in EEPROM\n");
410 /* validate checksum */
411 for (chksum = 0, i = 0; i < sizeof(*info)-2; i++)
413 if ((info->chksum[0] != chksum>>8) ||
414 (info->chksum[1] != (chksum&0xff))) {
415 puts("EEPROM: Failed EEPROM checksum\n");
420 /* original GW5400-A prototype */
421 baseboard = info->model[3];
422 if (strncasecmp((const char *)info->model, "GW5400-A", 8) == 0)
426 case '0': /* original GW5400-A prototype */
442 printf("EEPROM: Unknown model in EEPROM: %s\n", info->model);
450 * Baseboard specific GPIO
453 /* common to add baseboards */
454 static iomux_v3_cfg_t const gw_gpio_pads[] = {
456 MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
458 MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
462 static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
464 MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
466 MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
468 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
470 MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL),
472 MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
474 MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
476 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
478 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
480 MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
482 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
485 static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
487 MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
489 MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
491 MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
493 MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
496 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
498 MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
500 MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
503 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
505 MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
507 MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
509 MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
511 MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
514 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
516 MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
518 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
520 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
522 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
525 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
527 MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
529 MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
531 MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
533 MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
536 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
538 MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
540 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
542 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
545 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
547 MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
549 MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
551 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
553 MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
555 MX6_PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
557 MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
559 MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
561 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
563 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
565 MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
567 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
571 * each baseboard has 4 user configurable Digital IO lines which can
572 * be pinmuxed as a GPIO or in some cases a PWM
575 iomux_v3_cfg_t gpio_padmux;
577 iomux_v3_cfg_t pwm_padmux;
583 iomux_v3_cfg_t const *gpio_pads;
586 struct dio_cfg dio_cfg[4];
587 /* various gpios (0 if non-existent) */
600 struct ventana gpio_cfg[] = {
603 .gpio_pads = gw54xx_gpio_pads,
604 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads),
606 { MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9),
607 MX6_PAD_GPIO_9__PWM1_OUT, 1 },
608 { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
609 MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
610 { MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9),
611 MX6_PAD_SD4_DAT1__PWM3_OUT, 3 },
612 { MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10),
613 MX6_PAD_SD4_DAT2__PWM4_OUT, 4 },
620 .pcie_rst = IMX_GPIO_NR(1, 29),
621 .mezz_pwren = IMX_GPIO_NR(4, 7),
622 .mezz_irq = IMX_GPIO_NR(4, 9),
623 .rs485en = IMX_GPIO_NR(3, 24),
624 .dioi2c_en = IMX_GPIO_NR(4, 5),
625 .pcie_sson = IMX_GPIO_NR(1, 20),
630 .gpio_pads = gw51xx_gpio_pads,
631 .num_pads = ARRAY_SIZE(gw51xx_gpio_pads),
633 { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
635 { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
636 MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
637 { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
638 MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
639 { MX6_PAD_SD1_CMD__GPIO1_IO18, IMX_GPIO_NR(1, 18),
640 MX6_PAD_SD1_CMD__PWM4_OUT, 4 },
646 .pcie_rst = IMX_GPIO_NR(1, 0),
647 .mezz_pwren = IMX_GPIO_NR(2, 19),
648 .mezz_irq = IMX_GPIO_NR(2, 18),
649 .gps_shdn = IMX_GPIO_NR(1, 2),
650 .vidin_en = IMX_GPIO_NR(5, 20),
655 .gpio_pads = gw52xx_gpio_pads,
656 .num_pads = ARRAY_SIZE(gw52xx_gpio_pads),
658 { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
660 { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
661 MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
662 { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
663 MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
664 { MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20),
672 .pcie_rst = IMX_GPIO_NR(1, 29),
673 .mezz_pwren = IMX_GPIO_NR(2, 19),
674 .mezz_irq = IMX_GPIO_NR(2, 18),
675 .gps_shdn = IMX_GPIO_NR(1, 27),
676 .vidin_en = IMX_GPIO_NR(3, 31),
677 .usb_sel = IMX_GPIO_NR(1, 2),
682 .gpio_pads = gw53xx_gpio_pads,
683 .num_pads = ARRAY_SIZE(gw53xx_gpio_pads),
685 { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
687 { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
688 MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
689 { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
690 MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
691 { MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20),
699 .pcie_rst = IMX_GPIO_NR(1, 29),
700 .mezz_pwren = IMX_GPIO_NR(2, 19),
701 .mezz_irq = IMX_GPIO_NR(2, 18),
702 .gps_shdn = IMX_GPIO_NR(1, 27),
703 .vidin_en = IMX_GPIO_NR(3, 31),
708 .gpio_pads = gw54xx_gpio_pads,
709 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads),
711 { MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9),
712 MX6_PAD_GPIO_9__PWM1_OUT, 1 },
713 { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
714 MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
715 { MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9),
716 MX6_PAD_SD4_DAT1__PWM3_OUT, 3 },
717 { MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10),
718 MX6_PAD_SD4_DAT2__PWM4_OUT, 4 },
725 .pcie_rst = IMX_GPIO_NR(1, 29),
726 .mezz_pwren = IMX_GPIO_NR(2, 19),
727 .mezz_irq = IMX_GPIO_NR(2, 18),
728 .rs485en = IMX_GPIO_NR(7, 1),
729 .vidin_en = IMX_GPIO_NR(3, 31),
730 .dioi2c_en = IMX_GPIO_NR(4, 5),
731 .pcie_sson = IMX_GPIO_NR(1, 20),
735 /* setup GPIO pinmux and default configuration per baseboard */
736 static void setup_board_gpio(int board)
738 struct ventana_board_info *info = &ventana_info;
743 int quiet = simple_strtol(getenv("quiet"), NULL, 10);
745 if (board >= GW_UNKNOWN)
749 gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
752 if (is_cpu_type(MXC_CPU_MX6Q) &&
753 test_bit(EECONFIG_SATA, info->config)) {
754 gpio_direction_output(GP_MSATA_SEL,
755 (hwconfig("msata")) ? 1 : 0);
757 gpio_direction_output(GP_MSATA_SEL, 0);
761 * assert PCI_RST# (released by OS when clock is valid)
762 * TODO: figure out why leaving this de-asserted from PCI scan on boot
763 * causes linux pcie driver to hang during enumeration
765 gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
767 /* turn off (active-high) user LED's */
768 for (i = 0; i < 4; i++) {
769 if (gpio_cfg[board].leds[i])
770 gpio_direction_output(gpio_cfg[board].leds[i], 1);
773 /* Expansion Mezzanine IO */
774 gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
775 gpio_direction_input(gpio_cfg[board].mezz_irq);
777 /* RS485 Transmit Enable */
778 if (gpio_cfg[board].rs485en)
779 gpio_direction_output(gpio_cfg[board].rs485en, 0);
782 if (gpio_cfg[board].gps_shdn)
783 gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
785 /* Analog video codec power enable */
786 if (gpio_cfg[board].vidin_en)
787 gpio_direction_output(gpio_cfg[board].vidin_en, 1);
790 if (gpio_cfg[board].dioi2c_en)
791 gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
793 /* PCICK_SSON: disable spread-spectrum clock */
794 if (gpio_cfg[board].pcie_sson)
795 gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
797 /* USBOTG Select (PCISKT or FrontPanel) */
798 if (gpio_cfg[board].usb_sel)
799 gpio_direction_output(gpio_cfg[board].usb_sel, 0);
802 * Configure DIO pinmux/padctl registers
803 * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
805 for (i = 0; i < 4; i++) {
806 struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
807 unsigned ctrl = DIO_PAD_CTRL;
809 sprintf(arg, "dio%d", i);
812 s = hwconfig_subarg(arg, "padctrl", &len);
814 ctrl = simple_strtoul(s, NULL, 16) & 0x3ffff;
815 if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
817 printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i,
818 (cfg->gpio_param/32)+1,
822 imx_iomux_v3_setup_pad(cfg->gpio_padmux |
824 gpio_direction_input(cfg->gpio_param);
825 } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
828 printf("DIO%d: pwm%d\n", i, cfg->pwm_param);
829 imx_iomux_v3_setup_pad(cfg->pwm_padmux |
835 if (is_cpu_type(MXC_CPU_MX6Q) &&
836 (test_bit(EECONFIG_SATA, info->config))) {
837 printf("MSATA: %s\n", (hwconfig("msata") ?
838 "enabled" : "disabled"));
840 printf("RS232: %s\n", (hwconfig("rs232")) ?
841 "enabled" : "disabled");
845 #if defined(CONFIG_CMD_PCI)
846 int imx6_pcie_toggle_reset(void)
848 if (board_type < GW_UNKNOWN) {
849 gpio_direction_output(gpio_cfg[board_type].pcie_rst, 0);
851 gpio_direction_output(gpio_cfg[board_type].pcie_rst, 1);
855 #endif /* CONFIG_CMD_PCI */
857 #ifdef CONFIG_SERIAL_TAG
859 * called when setting up ATAGS before booting kernel
860 * populate serialnum from the following (in order of priority):
864 void get_board_serial(struct tag_serialnr *serialnr)
866 char *serial = getenv("serial#");
870 serialnr->low = simple_strtoul(serial, NULL, 10);
871 } else if (ventana_info.model[0]) {
873 serialnr->low = ventana_info.serial;
885 int board_early_init_f(void)
888 gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
895 gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
896 CONFIG_DDR_MB*1024*1024);
903 struct iomuxc_base_regs *const iomuxc_regs
904 = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
906 clrsetbits_le32(&iomuxc_regs->gpr[1],
907 IOMUXC_GPR1_OTG_ID_MASK,
908 IOMUXC_GPR1_OTG_ID_GPIO1);
910 /* address of linux boot parameters */
911 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
913 #ifdef CONFIG_CMD_NAND
916 #ifdef CONFIG_MXC_SPI
919 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
920 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
921 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
923 #ifdef CONFIG_CMD_SATA
926 /* read Gateworks EEPROM into global struct (used later) */
927 board_type = read_eeprom();
929 /* board-specifc GPIO iomux */
930 if (board_type < GW_UNKNOWN) {
931 imx_iomux_v3_setup_multiple_pads(gw_gpio_pads,
932 ARRAY_SIZE(gw_gpio_pads));
933 imx_iomux_v3_setup_multiple_pads(gpio_cfg[board_type].gpio_pads,
934 gpio_cfg[board_type].num_pads);
940 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
942 * called during late init (after relocation and after board_init())
943 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
948 struct ventana_board_info *info = &ventana_info;
949 unsigned char buf[4];
951 int quiet; /* Quiet or minimal output mode */
956 quiet = simple_strtol(p, NULL, 10);
958 setenv("quiet", "0");
960 puts("\nGateworks Corporation Copyright 2014\n");
961 if (info->model[0]) {
962 printf("Model: %s\n", info->model);
963 printf("MFGDate: %02x-%02x-%02x%02x\n",
964 info->mfgdate[0], info->mfgdate[1],
965 info->mfgdate[2], info->mfgdate[3]);
966 printf("Serial:%d\n", info->serial);
968 puts("Invalid EEPROM - board will not function fully\n");
973 /* Display GSC firmware revision/CRC/status */
974 i2c_set_bus_num(I2C_GSC);
975 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) {
976 printf("GSC: v%d", buf[0]);
977 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) {
978 printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */
979 printf(" 0x%02x", buf[0]); /* irq status */
984 if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
986 buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
993 #ifdef CONFIG_CMD_BMODE
995 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
996 * see Table 8-11 and Table 5-9
997 * BOOT_CFG1[7] = 1 (boot from NAND)
998 * BOOT_CFG1[5] = 0 - raw NAND
999 * BOOT_CFG1[4] = 0 - default pad settings
1000 * BOOT_CFG1[3:2] = 00 - devices = 1
1001 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
1002 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
1003 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
1004 * BOOT_CFG2[0] = 0 - Reset time 12ms
1006 static const struct boot_mode board_boot_modes[] = {
1007 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
1008 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
1014 int misc_init_r(void)
1016 struct ventana_board_info *info = &ventana_info;
1019 /* set env vars based on EEPROM data */
1020 if (ventana_info.model[0]) {
1021 char str[16], fdt[36];
1023 const char *cputype = "";
1027 * FDT name will be prefixed with CPU type. Three versions
1028 * will be created each increasingly generic and bootloader
1029 * env scripts will try loading each from most specific to
1032 if (is_cpu_type(MXC_CPU_MX6Q))
1034 else if (is_cpu_type(MXC_CPU_MX6DL))
1036 memset(str, 0, sizeof(str));
1037 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
1038 str[i] = tolower(info->model[i]);
1039 if (!getenv("model"))
1040 setenv("model", str);
1041 if (!getenv("fdt_file")) {
1042 sprintf(fdt, "%s-%s.dtb", cputype, str);
1043 setenv("fdt_file", fdt);
1045 p = strchr(str, '-');
1049 setenv("model_base", str);
1050 if (!getenv("fdt_file1")) {
1051 sprintf(fdt, "%s-%s.dtb", cputype, str);
1052 setenv("fdt_file1", fdt);
1057 if (!getenv("fdt_file2")) {
1058 sprintf(fdt, "%s-%s.dtb", cputype, str);
1059 setenv("fdt_file2", fdt);
1063 /* initialize env from EEPROM */
1064 if (test_bit(EECONFIG_ETH0, info->config) &&
1065 !getenv("ethaddr")) {
1066 eth_setenv_enetaddr("ethaddr", info->mac0);
1068 if (test_bit(EECONFIG_ETH1, info->config) &&
1069 !getenv("eth1addr")) {
1070 eth_setenv_enetaddr("eth1addr", info->mac1);
1073 /* board serial-number */
1074 sprintf(str, "%6d", info->serial);
1075 setenv("serial#", str);
1078 /* configure PFUZE100 PMIC (not used on all Ventana baseboards) */
1079 power_pfuze100_init(I2C_PMIC);
1080 if (board_type == GW54xx || board_type == GW54proto) {
1081 struct pmic *p = pmic_get("PFUZE100_PMIC");
1084 if (p && !pmic_probe(p)) {
1085 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
1086 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
1088 /* Set VGEN1 to 1.5V and enable */
1089 pmic_reg_read(p, PFUZE100_VGEN1VOL, ®);
1090 reg &= ~(LDO_VOL_MASK);
1091 reg |= (LDOA_1_50V | LDO_EN);
1092 pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
1094 /* Set SWBST to 5.0V and enable */
1095 pmic_reg_read(p, PFUZE100_SWBSTCON1, ®);
1096 reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
1097 reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
1098 pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
1102 /* setup baseboard specific GPIO pinmux and config */
1103 setup_board_gpio(board_type);
1105 #ifdef CONFIG_CMD_BMODE
1106 add_board_boot_modes(board_boot_modes);
1110 * The Gateworks System Controller implements a boot
1111 * watchdog (always enabled) as a workaround for IMX6 boot related
1113 * ERR005768 - no fix
1114 * ERR006282 - fixed in silicon r1.3
1115 * ERR007117 - fixed in silicon r1.3
1116 * ERR007220 - fixed in silicon r1.3
1117 * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
1119 * Disable the boot watchdog and display/clear the timeout flag if set
1121 i2c_set_bus_num(I2C_GSC);
1122 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) {
1123 reg |= (1 << GSC_SC_CTRL1_WDDIS);
1124 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
1125 puts("Error: could not disable GSC Watchdog\n");
1127 puts("Error: could not disable GSC Watchdog\n");
1129 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1)) {
1130 if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */
1131 puts("GSC boot watchdog timeout detected");
1132 reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */
1133 gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1);
1140 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1142 /* FDT aliases associated with EEPROM config bits */
1143 const char *fdt_aliases[] = {
1211 * called prior to booting kernel or by 'fdt boardsetup' command
1213 * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1214 * - mtd partitions based on mtdparts/mtdids env
1215 * - system-serial (board serial num from EEPROM)
1216 * - board (full model from EEPROM)
1217 * - peripherals removed from DTB if not loaded on board (per EEPROM config)
1219 void ft_board_setup(void *blob, bd_t *bd)
1222 struct ventana_board_info *info = &ventana_info;
1223 struct node_info nodes[] = {
1224 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
1225 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
1227 const char *model = getenv("model");
1229 if (getenv("fdt_noauto")) {
1230 puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
1234 /* Update partition nodes using info from mtdparts env var */
1235 puts(" Updating MTD partitions...\n");
1236 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1239 puts("invalid board info: Leaving FDT fully enabled\n");
1242 printf(" Adjusting FDT per EEPROM for %s...\n", model);
1244 /* board serial number */
1245 fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
1246 strlen(getenv("serial#") + 1));
1248 /* board (model contains model from device-tree) */
1249 fdt_setprop(blob, 0, "board", info->model,
1250 strlen((const char *)info->model) + 1);
1253 * Peripheral Config:
1254 * remove nodes by alias path if EEPROM config tells us the
1255 * peripheral is not loaded on the board.
1257 for (bit = 0; bit < 64; bit++) {
1258 if (!test_bit(bit, info->config))
1259 fdt_del_node_and_alias(blob, fdt_aliases[bit]);
1262 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */