2 * Copyright (C) 2013 Gateworks Corporation
4 * Author: Tim Harvey <tharvey@gateworks.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/ctype.h>
17 * The Gateworks System Controller will fail to ACK a master transaction if
18 * it is busy, which can occur during its 1HZ timer tick while reading ADC's.
19 * When this does occur, it will never be busy long enough to fail more than
20 * 2 back-to-back transfers. Thus we wrap i2c_read and i2c_write with
23 int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
30 ret = i2c_read(chip, addr, alen, buf, len);
33 debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
42 int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
49 ret = i2c_write(chip, addr, alen, buf, len);
52 debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
62 static void read_hwmon(const char *name, uint reg, uint size)
67 printf("%-8s:", name);
68 memset(buf, 0, sizeof(buf));
69 if (gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, size)) {
72 ui = buf[0] | (buf[1]<<8) | (buf[2]<<16);
80 int gsc_info(int verbose)
82 const char *model = getenv("model");
83 unsigned char buf[16];
86 if (gsc_i2c_read(GSC_SC_ADDR, 0, 1, buf, 16))
87 return CMD_RET_FAILURE;
89 printf("GSC: v%d", buf[GSC_SC_FWVER]);
90 printf(" 0x%04x", buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC+1]<<8);
91 printf(" WDT:%sabled", (buf[GSC_SC_CTRL1] & (1<<GSC_SC_CTRL1_WDEN))
93 if (buf[GSC_SC_STATUS] & (1 << GSC_SC_IRQ_WATCHDOG)) {
94 buf[GSC_SC_STATUS] &= ~(1 << GSC_SC_IRQ_WATCHDOG);
96 gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1,
97 &buf[GSC_SC_STATUS], 1);
101 return CMD_RET_SUCCESS;
103 read_hwmon("Temp", GSC_HWMON_TEMP, 2);
104 read_hwmon("VIN", GSC_HWMON_VIN, 3);
105 read_hwmon("VBATT", GSC_HWMON_VBATT, 3);
106 read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3);
107 read_hwmon("VDD_ARM", GSC_HWMON_VDD_CORE, 3);
108 read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3);
109 read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3);
110 read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3);
111 read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3);
112 read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3);
113 read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3);
114 read_hwmon("VDD_IO2", GSC_HWMON_VDD_IO2, 3);
116 case '1': /* GW51xx */
117 read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */
119 case '2': /* GW52xx */
121 case '3': /* GW53xx */
122 read_hwmon("VDD_IO4", GSC_HWMON_VDD_IO4, 3); /* -C rev */
123 read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3);
125 case '4': /* GW54xx */
126 read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */
127 read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3);
129 case '5': /* GW55xx */
135 #ifdef CONFIG_CMD_GSC
136 static int do_gsc_wd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
141 return CMD_RET_USAGE;
143 if (strcasecmp(argv[1], "enable") == 0) {
147 timeout = simple_strtoul(argv[2], NULL, 10);
149 if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
150 return CMD_RET_FAILURE;
151 reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME));
153 reg |= (1 << GSC_SC_CTRL1_WDTIME);
156 reg |= (1 << GSC_SC_CTRL1_WDEN);
157 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
158 return CMD_RET_FAILURE;
159 printf("GSC Watchdog enabled with timeout=%d seconds\n",
161 } else if (strcasecmp(argv[1], "disable") == 0) {
163 if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
164 return CMD_RET_FAILURE;
165 reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME));
166 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
167 return CMD_RET_FAILURE;
168 printf("GSC Watchdog disabled\n");
170 return CMD_RET_USAGE;
172 return CMD_RET_SUCCESS;
175 static int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
180 if (strcasecmp(argv[1], "wd") == 0)
181 return do_gsc_wd(cmdtp, flag, --argc, ++argv);
183 return CMD_RET_USAGE;
187 gsc, 4, 1, do_gsc, "GSC configuration",
188 "[wd enable [30|60]]|[wd disable]\n"
191 #endif /* CONFIG_CMD_GSC */