2 * Linker script for Gaisler Research AB's Template design
3 * for Altera NIOS Development board Stratix II Edition, EP2S60 FPGA.
6 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
8 * SPDX-License-Identifier: GPL-2.0+
11 OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
17 /* Read-only sections, merged into text segment: */
19 .interp : { *(.interp) }
21 .dynsym : { *(.dynsym) }
22 .dynstr : { *(.dynstr) }
23 .rel.text : { *(.rel.text) }
24 .rela.text : { *(.rela.text) }
25 .rel.data : { *(.rel.data) }
26 .rela.data : { *(.rela.data) }
27 .rel.rodata : { *(.rel.rodata) }
28 .rela.rodata : { *(.rela.rodata) }
29 .rel.got : { *(.rel.got) }
30 .rela.got : { *(.rela.got) }
31 .rel.ctors : { *(.rel.ctors) }
32 .rela.ctors : { *(.rela.ctors) }
33 .rel.dtors : { *(.rel.dtors) }
34 .rela.dtors : { *(.rela.dtors) }
35 .rel.bss : { *(.rel.bss) }
36 .rela.bss : { *(.rela.bss) }
37 .rel.plt : { *(.rel.plt) }
38 .rela.plt : { *(.rela.plt) }
47 arch/sparc/cpu/leon3/start.o (.text)
48 /* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
50 /* PROM CODE, Will be relocated to the end of memory,
51 * no global data accesses please.
65 *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
75 KEEP(*(SORT(.u_boot_list*)));
102 /* .data.rel : { } */
106 .text.init : { *(.text.init) }
107 .data.init : { *(.data.init) }
118 . = ALIGN(16); /* to speed clearing of bss up */
124 /* Relocated into main memory */
126 /* Start of main memory */
129 .stack (NOLOAD) : { *(.stack) }
133 /* global data in RAM passed to kernel after booting */
135 .stab 0 : { *(.stab) }
136 .stabstr 0 : { *(.stabstr) }
137 .stab.excl 0 : { *(.stab.excl) }
138 .stab.exclstr 0 : { *(.stab.exclstr) }
139 .stab.index 0 : { *(.stab.index) }
140 .stab.indexstr 0 : { *(.stab.indexstr) }
141 .comment 0 : { *(.comment) }