3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
28 #define MEM_MCOPT1_INIT_VAL 0x00800000
29 #define MEM_RTR_INIT_VAL 0x04070000
30 #define MEM_PMIT_INIT_VAL 0x07c00000
31 #define MEM_MB0CF_INIT_VAL 0x00082001
32 #define MEM_MB1CF_INIT_VAL 0x04082000
33 #define MEM_SDTR1_INIT_VAL 0x00854005
34 #define SDRAM0_CFG_ENABLE 0x80000000
36 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 MB */
38 int board_early_init_f (void)
41 mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
42 mtdcr (UIC0ER, 0x00000000); /* disable all ints */
43 mtdcr (UIC0CR, 0x00000010);
44 mtdcr (UIC0PR, 0xFFFF7FF0); /* set int polarities */
45 mtdcr (UIC0TR, 0x00000010); /* set int trigger levels */
46 mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
48 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
49 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
50 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
51 mtdcr(UIC0PR, 0xFFFFFFF0); /* set int polarities */
52 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
53 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
54 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
59 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
61 mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
68 int misc_init_f (void)
70 return 0; /* dummy implementation */
74 int misc_init_r (void)
76 #if defined(CONFIG_CMD_NAND)
78 * Set NAND-FLASH GPIO signals to default
80 out32(GPIO0_OR, in32(GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
81 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CE);
89 * Check Board Identity:
94 int i = getenv_r ("serial#", str, sizeof(str));
99 puts ("### No HW ID - assuming G2000");
110 /* -------------------------------------------------------------------------
111 G2000 rev B is an embeded design. we don't read for spd of this version.
112 Doing static SDRAM controller configuration in the following section.
113 ------------------------------------------------------------------------- */
115 long int init_sdram_static_settings(void)
117 #define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data)
118 /* disable memcontroller so updates work */
119 mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL );
120 mtsdram0( mem_rtr , MEM_RTR_INIT_VAL );
121 mtsdram0( mem_pmit , MEM_PMIT_INIT_VAL );
122 mtsdram0( mem_mb0cf , MEM_MB0CF_INIT_VAL );
123 mtsdram0( mem_mb1cf , MEM_MB1CF_INIT_VAL );
124 mtsdram0( mem_sdtr1 , MEM_SDTR1_INIT_VAL );
126 /* SDRAM have a power on delay, 500 micro should do */
128 mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE );
130 return (CONFIG_SYS_SDRAM_SIZE); /* CONFIG_SYS_SDRAM_SIZE is in G2000.h */
134 phys_size_t initdram (int board_type)
138 /* flzt, we can still turn this on in the future */
139 /* #ifdef CONFIG_SPD_EEPROM
142 ret = init_sdram_static_settings();
146 ret = init_sdram_static_settings();
151 #if 0 /* test-only !!! */
152 int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
156 printf("\nEBC registers for PPC405GP:\n");
157 mfebc(PB0AP, ap); mfebc(PB0CR, cr);
158 printf("0: AP=%08lx CP=%08lx\n", ap, cr);
159 mfebc(PB1AP, ap); mfebc(PB1CR, cr);
160 printf("1: AP=%08lx CP=%08lx\n", ap, cr);
161 mfebc(PB2AP, ap); mfebc(PB2CR, cr);
162 printf("2: AP=%08lx CP=%08lx\n", ap, cr);
163 mfebc(PB3AP, ap); mfebc(PB3CR, cr);
164 printf("3: AP=%08lx CP=%08lx\n", ap, cr);
165 mfebc(PB4AP, ap); mfebc(PB4CR, cr);
166 printf("4: AP=%08lx CP=%08lx\n", ap, cr);
172 dumpebc, 1, 1, do_dumpebc,
173 "Dump all EBC registers",
178 int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
182 printf("\nDevice Configuration Registers (DCR's) for PPC405GP:");
183 for (i=0; i<=0x1e0; i++) {
185 printf("\n%04x ", i);
187 printf("%08lx ", get_dcr(i));
194 dumpdcr, 1, 1, do_dumpdcr,
195 "Dump all DCR registers",
200 int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
202 printf("\nSpecial Purpose Registers (SPR's) for PPC405GP:");
203 printf("\n%04x %08x ", 947, mfspr(947));
204 printf("\n%04x %08x ", 9, mfspr(9));
205 printf("\n%04x %08x ", 1014, mfspr(1014));
206 printf("\n%04x %08x ", 1015, mfspr(1015));
207 printf("\n%04x %08x ", 1010, mfspr(1010));
208 printf("\n%04x %08x ", 957, mfspr(957));
209 printf("\n%04x %08x ", 1008, mfspr(1008));
210 printf("\n%04x %08x ", 1018, mfspr(1018));
211 printf("\n%04x %08x ", 954, mfspr(954));
212 printf("\n%04x %08x ", 950, mfspr(950));
213 printf("\n%04x %08x ", 951, mfspr(951));
214 printf("\n%04x %08x ", 981, mfspr(981));
215 printf("\n%04x %08x ", 980, mfspr(980));
216 printf("\n%04x %08x ", 982, mfspr(982));
217 printf("\n%04x %08x ", 1012, mfspr(1012));
218 printf("\n%04x %08x ", 1013, mfspr(1013));
219 printf("\n%04x %08x ", 948, mfspr(948));
220 printf("\n%04x %08x ", 949, mfspr(949));
221 printf("\n%04x %08x ", 1019, mfspr(1019));
222 printf("\n%04x %08x ", 979, mfspr(979));
223 printf("\n%04x %08x ", 8, mfspr(8));
224 printf("\n%04x %08x ", 945, mfspr(945));
225 printf("\n%04x %08x ", 987, mfspr(987));
226 printf("\n%04x %08x ", 287, mfspr(287));
227 printf("\n%04x %08x ", 953, mfspr(953));
228 printf("\n%04x %08x ", 955, mfspr(955));
229 printf("\n%04x %08x ", 272, mfspr(272));
230 printf("\n%04x %08x ", 273, mfspr(273));
231 printf("\n%04x %08x ", 274, mfspr(274));
232 printf("\n%04x %08x ", 275, mfspr(275));
233 printf("\n%04x %08x ", 260, mfspr(260));
234 printf("\n%04x %08x ", 276, mfspr(276));
235 printf("\n%04x %08x ", 261, mfspr(261));
236 printf("\n%04x %08x ", 277, mfspr(277));
237 printf("\n%04x %08x ", 262, mfspr(262));
238 printf("\n%04x %08x ", 278, mfspr(278));
239 printf("\n%04x %08x ", 263, mfspr(263));
240 printf("\n%04x %08x ", 279, mfspr(279));
241 printf("\n%04x %08x ", 26, mfspr(26));
242 printf("\n%04x %08x ", 27, mfspr(27));
243 printf("\n%04x %08x ", 990, mfspr(990));
244 printf("\n%04x %08x ", 991, mfspr(991));
245 printf("\n%04x %08x ", 956, mfspr(956));
246 printf("\n%04x %08x ", 284, mfspr(284));
247 printf("\n%04x %08x ", 285, mfspr(285));
248 printf("\n%04x %08x ", 986, mfspr(986));
249 printf("\n%04x %08x ", 984, mfspr(984));
250 printf("\n%04x %08x ", 256, mfspr(256));
251 printf("\n%04x %08x ", 1, mfspr(1));
252 printf("\n%04x %08x ", 944, mfspr(944));
258 dumpspr, 1, 1, do_dumpspr,
259 "Dump all SPR registers",