2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * Author: Chunhe Lan <Chunhe.Lan@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <environment.h>
17 #include <fsl_esdhc.h>
22 #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
24 DECLARE_GLOBAL_DATA_PTR;
26 phys_size_t get_effective_memsize(void)
28 return CONFIG_SYS_L3_SIZE;
31 unsigned long get_board_sys_clk(void)
33 return CONFIG_SYS_CLK_FREQ;
36 unsigned long get_board_ddr_clk(void)
38 return CONFIG_DDR_CLK_FREQ;
41 void board_init_f(ulong bootflag)
43 u32 plat_ratio, sys_clk, ccb_clk;
44 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
46 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
47 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
49 /* Update GD pointer */
50 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
52 /* compiler optimization barrier needed for GCC >= 3.4 */
53 __asm__ __volatile__("" : : : "memory");
57 /* initialize selected port with appropriate baud rate */
58 sys_clk = get_board_sys_clk();
59 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
60 ccb_clk = sys_clk * plat_ratio / 2;
62 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
63 ccb_clk / 16 / CONFIG_BAUDRATE);
65 puts("\nSD boot...\n");
67 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
70 void board_init_r(gd_t *gd, ulong dest_addr)
74 bd = (bd_t *)(gd + sizeof(gd_t));
75 memset(bd, 0, sizeof(bd_t));
77 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
78 bd->bi_memsize = CONFIG_SYS_L3_SIZE;
82 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
83 CONFIG_SPL_RELOC_MALLOC_SIZE);
84 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
87 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
88 (uchar *)CONFIG_ENV_ADDR);
90 gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
91 gd->env_valid = ENV_VALID;