board/freescale/t4qds/tlb.c

   1 /*
   2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2000
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/mmu.h>
  12
  13 struct fsl_e_tlb_entry tlb_table[] = {
  14         /* TLB 0 - for temp stack in cache */
  15         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  16                       CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  17                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  18                       0, 0, BOOKE_PAGESZ_4K, 0),
  19         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  20                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  21                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  22                       0, 0, BOOKE_PAGESZ_4K, 0),
  23         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  24                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  25                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  26                       0, 0, BOOKE_PAGESZ_4K, 0),
  27         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  28                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  29                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  30                       0, 0, BOOKE_PAGESZ_4K, 0),
  31
  32         /* TLB 1 */
  33         /* *I*** - Covers boot page */
  34 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
  35         /*
  36          * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
  37          * SRAM is at 0xfff00000, it covered the 0xfffff000.
  38          */
  39         SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
  40                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  41                         0, 0, BOOKE_PAGESZ_1M, 1),
  42 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  43         /*
  44          * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
  45          * space is at 0xfff00000, it covered the 0xfffff000.
  46          */
  47         SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
  48                       CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
  49                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
  50                       0, 0, BOOKE_PAGESZ_1M, 1),
  51 #else
  52         SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  53                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  54                       0, 0, BOOKE_PAGESZ_4K, 1),
  55 #endif
  56
  57         /* *I*G* - CCSRBAR */
  58         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  59                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  60                       0, 1, BOOKE_PAGESZ_16M, 1),
  61
  62         /* *I*G* - Flash, localbus */
  63         /* This will be changed to *I*G* after relocation to RAM. */
  64         SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  65                       MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  66                       0, 2, BOOKE_PAGESZ_256M, 1),
  67 #ifndef CONFIG_SPL_BUILD
  68         /* *I*G* - PCI */
  69         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  70                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  71                       0, 3, BOOKE_PAGESZ_1G, 1),
  72
  73         /* *I*G* - PCI */
  74         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
  75                       CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
  76                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  77                       0, 4, BOOKE_PAGESZ_256M, 1),
  78
  79         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
  80                       CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
  81                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  82                       0, 5, BOOKE_PAGESZ_256M, 1),
  83
  84         /* *I*G* - PCI I/O */
  85         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  86                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  87                       0, 6, BOOKE_PAGESZ_256K, 1),
  88
  89         /* Bman/Qman */
  90 #ifdef CONFIG_SYS_BMAN_MEM_PHYS
  91         SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
  92                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  93                       0, 9, BOOKE_PAGESZ_16M, 1),
  94         SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
  95                       CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
  96                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  97                       0, 10, BOOKE_PAGESZ_16M, 1),
  98 #endif
  99 #ifdef CONFIG_SYS_QMAN_MEM_PHYS
 100         SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
 101                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
 102                       0, 11, BOOKE_PAGESZ_16M, 1),
 103         SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
 104                       CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
 105                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 106                       0, 12, BOOKE_PAGESZ_16M, 1),
 107 #endif
 108 #endif
 109 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 110         SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
 111                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 112                       0, 13, BOOKE_PAGESZ_32M, 1),
 113 #endif
 114 #ifdef CONFIG_SYS_NAND_BASE
 115         /*
 116          * *I*G - NAND
 117          * entry 14 and 15 has been used hard coded, they will be disabled
 118          * in cpu_init_f, so we use entry 16 for nand.
 119          */
 120         SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 121                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 122                         0, 16, BOOKE_PAGESZ_64K, 1),
 123 #endif
 124 #ifdef QIXIS_BASE_PHYS
 125         SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
 126                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 127                       0, 17, BOOKE_PAGESZ_4K, 1),
 128 #endif
 129 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 130         /*
 131          * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
 132          * fetching ucode and ENV from master
 133          */
 134         SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
 135                       CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 136                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
 137                       0, 18, BOOKE_PAGESZ_1M, 1),
 138 #endif
 139
 140 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
 141         SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 142                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 143                       0, 19, BOOKE_PAGESZ_2G, 1)
 144 #endif
 145 };
 146
 147 int num_tlb_entries = ARRAY_SIZE(tlb_table);