2 * Copyright 2009-2012 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <linux/compiler.h>
29 #include <asm/processor.h>
30 #include <asm/cache.h>
31 #include <asm/immap_85xx.h>
32 #include <asm/fsl_law.h>
33 #include <asm/fsl_serdes.h>
34 #include <asm/fsl_portals.h>
35 #include <asm/fsl_liodn.h>
38 #include "../common/qixis.h"
39 #include "../common/vsc3316_3308.h"
41 #include "t4240qds_qixis.h"
43 DECLARE_GLOBAL_DATA_PTR;
48 struct cpu_type *cpu = gd->cpu;
49 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
52 printf("Board: %sQDS, ", cpu->name);
53 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
54 QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
56 sw = QIXIS_READ(brdcfg[0]);
57 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
60 printf("vBank: %d\n", sw);
66 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
68 /* Display the RCW, so that no one gets confused as to what RCW
69 * we're actually using for this boot.
71 puts("Reset Configuration Word (RCW):");
72 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
73 u32 rcw = in_be32(&gur->rcwsr[i]);
76 printf("\n %08x:", i * 4);
82 * Display the actual SERDES reference clocks as configured by the
83 * dip switches on the board. Note that the SWx registers could
84 * technically be set to force the reference clocks to match the
85 * values that the SERDES expects (or vice versa). For now, however,
86 * we just display both values and hope the user notices when they
89 puts("SERDES Reference Clocks: ");
90 sw = QIXIS_READ(brdcfg[2]);
91 for (i = 0; i < MAX_SERDES; i++) {
92 static const char *freq[] = {
93 "100", "125", "156.25", "161.1328125"};
94 unsigned int clock = (sw >> (2 * i)) & 3;
96 printf("SERDES%u=%sMHz ", i+1, freq[clock]);
103 int select_i2c_ch_pca9547(u8 ch)
107 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
109 puts("PCA: failed to select proper channel\n");
116 /* Configure Crossbar switches for Front-Side SerDes Ports */
117 int config_frontside_crossbar_vsc3316(void)
119 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
120 u32 srds_prtcl_s1, srds_prtcl_s2;
123 ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS);
127 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
128 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
129 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
131 ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
134 ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
139 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
140 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
141 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
143 ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
146 ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
154 int config_backside_crossbar_mux(void)
156 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
157 u32 srds_prtcl_s3, srds_prtcl_s4;
160 srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) &
161 FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
162 srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
163 switch (srds_prtcl_s3) {
165 /* SerDes3 is not enabled */
170 /* SD3(0:7) => SLOT5(0:7) */
171 brdcfg = QIXIS_READ(brdcfg[12]);
172 brdcfg &= ~BRDCFG12_SD3MX_MASK;
173 brdcfg |= BRDCFG12_SD3MX_SLOT5;
174 QIXIS_WRITE(brdcfg[12], brdcfg);
185 /* SD3(4:7) => SLOT6(0:3) */
186 brdcfg = QIXIS_READ(brdcfg[12]);
187 brdcfg &= ~BRDCFG12_SD3MX_MASK;
188 brdcfg |= BRDCFG12_SD3MX_SLOT6;
189 QIXIS_WRITE(brdcfg[12], brdcfg);
192 printf("WARNING: unsupported for SerDes3 Protocol %d\n",
197 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
198 FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
199 srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
200 switch (srds_prtcl_s4) {
202 /* SerDes4 is not enabled */
205 /* 10b, SD4(0:7) => SLOT7(0:7) */
206 brdcfg = QIXIS_READ(brdcfg[12]);
207 brdcfg &= ~BRDCFG12_SD4MX_MASK;
208 brdcfg |= BRDCFG12_SD4MX_SLOT7;
209 QIXIS_WRITE(brdcfg[12], brdcfg);
214 /* x1b, SD4(4:7) => SLOT8(0:3) */
215 brdcfg = QIXIS_READ(brdcfg[12]);
216 brdcfg &= ~BRDCFG12_SD4MX_MASK;
217 brdcfg |= BRDCFG12_SD4MX_SLOT8;
218 QIXIS_WRITE(brdcfg[12], brdcfg);
225 /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
226 brdcfg = QIXIS_READ(brdcfg[12]);
227 brdcfg &= ~BRDCFG12_SD4MX_MASK;
228 brdcfg |= BRDCFG12_SD4MX_AURO_SATA;
229 QIXIS_WRITE(brdcfg[12], brdcfg);
232 printf("WARNING: unsupported for SerDes4 Protocol %d\n",
240 int board_early_init_r(void)
242 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
243 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
246 * Remap Boot flash + PROMJET region to caching-inhibited
247 * so that flash can be erased properly.
250 /* Flush d-cache and invalidate i-cache of any FLASH data */
254 /* invalidate existing TLB entry for flash + promjet */
255 disable_tlb(flash_esel);
257 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
258 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
259 0, flash_esel, BOOKE_PAGESZ_256M, 1);
262 #ifdef CONFIG_SYS_DPAA_QBMAN
266 /* Disable remote I2C connectoin */
267 QIXIS_WRITE(brdcfg[5], BRDCFG5_RESET);
269 /* Configure board SERDES ports crossbar */
270 config_frontside_crossbar_vsc3316();
271 config_backside_crossbar_mux();
272 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
277 unsigned long get_board_sys_clk(void)
279 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
281 switch (sysclk_conf & 0x0F) {
282 case QIXIS_SYSCLK_83:
284 case QIXIS_SYSCLK_100:
286 case QIXIS_SYSCLK_125:
288 case QIXIS_SYSCLK_133:
290 case QIXIS_SYSCLK_150:
292 case QIXIS_SYSCLK_160:
294 case QIXIS_SYSCLK_166:
300 unsigned long get_board_ddr_clk(void)
302 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
304 switch ((ddrclk_conf & 0x30) >> 4) {
305 case QIXIS_DDRCLK_100:
307 case QIXIS_DDRCLK_125:
309 case QIXIS_DDRCLK_133:
315 static const char *serdes_clock_to_string(u32 clock)
318 case SRDS_PLLCR0_RFCK_SEL_100:
320 case SRDS_PLLCR0_RFCK_SEL_125:
322 case SRDS_PLLCR0_RFCK_SEL_156_25:
324 case SRDS_PLLCR0_RFCK_SEL_161_13:
325 return "161.1328125";
331 int misc_init_r(void)
334 serdes_corenet_t *srds_regs =
335 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
336 u32 actual[MAX_SERDES];
339 sw = QIXIS_READ(brdcfg[2]);
340 for (i = 0; i < MAX_SERDES; i++) {
341 unsigned int clock = (sw >> (2 * i)) & 3;
344 actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
347 actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
350 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
353 actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13;
358 for (i = 0; i < MAX_SERDES; i++) {
359 u32 pllcr0 = srds_regs->bank[i].pllcr0;
360 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
361 if (expected != actual[i]) {
362 printf("Warning: SERDES%u expects reference clock"
363 " %sMHz, but actual is %sMHz\n", i + 1,
364 serdes_clock_to_string(expected),
365 serdes_clock_to_string(actual[i]));
372 void ft_board_setup(void *blob, bd_t *bd)
377 ft_cpu_setup(blob, bd);
379 base = getenv_bootm_low();
380 size = getenv_bootm_size();
382 fdt_fixup_memory(blob, (u64)base, (u64)size);
385 pci_of_setup(blob, bd);
388 fdt_fixup_liodn(blob);
389 fdt_fixup_dr_usb(blob, bd);
391 #ifdef CONFIG_SYS_DPAA_FMAN
392 fdt_fixup_fman_ethernet(blob);
393 fdt_fixup_board_enet(blob);