1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright 2014 Freescale Semiconductor, Inc.
6 #include <clock_legacy.h>
8 #include <env_internal.h>
15 #include <fsl_esdhc.h>
17 #include "../common/qixis.h"
18 #include "t4240qds_qixis.h"
20 #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
22 DECLARE_GLOBAL_DATA_PTR;
24 phys_size_t get_effective_memsize(void)
26 return CONFIG_SYS_L3_SIZE;
29 unsigned long get_board_sys_clk(void)
31 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
33 switch (sysclk_conf & 0x0F) {
36 case QIXIS_SYSCLK_100:
38 case QIXIS_SYSCLK_125:
40 case QIXIS_SYSCLK_133:
42 case QIXIS_SYSCLK_150:
44 case QIXIS_SYSCLK_160:
46 case QIXIS_SYSCLK_166:
52 unsigned long get_board_ddr_clk(void)
54 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
56 switch ((ddrclk_conf & 0x30) >> 4) {
57 case QIXIS_DDRCLK_100:
59 case QIXIS_DDRCLK_125:
61 case QIXIS_DDRCLK_133:
67 void board_init_f(ulong bootflag)
69 u32 plat_ratio, sys_clk, ccb_clk;
70 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
71 #ifdef CONFIG_SPL_NAND_BOOT
75 #ifdef CONFIG_SPL_NAND_BOOT
76 porsr1 = in_be32(&gur->porsr1);
77 pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
78 out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
80 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
81 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
83 /* Update GD pointer */
84 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
86 /* compiler optimization barrier needed for GCC >= 3.4 */
87 __asm__ __volatile__("" : : : "memory");
91 /* initialize selected port with appropriate baud rate */
92 sys_clk = get_board_sys_clk();
93 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
94 ccb_clk = sys_clk * plat_ratio / 2;
96 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
97 ccb_clk / 16 / CONFIG_BAUDRATE);
99 #ifdef CONFIG_SPL_MMC_BOOT
100 puts("\nSD boot...\n");
101 #elif defined(CONFIG_SPL_NAND_BOOT)
102 puts("\nNAND boot...\n");
104 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
107 void board_init_r(gd_t *gd, ulong dest_addr)
111 bd = (bd_t *)(gd + sizeof(gd_t));
112 memset(bd, 0, sizeof(bd_t));
114 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
115 bd->bi_memsize = CONFIG_SYS_L3_SIZE;
119 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
120 CONFIG_SPL_RELOC_MALLOC_SIZE);
121 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
123 #ifdef CONFIG_SPL_NAND_BOOT
124 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
125 (uchar *)SPL_ENV_ADDR);
127 #ifdef CONFIG_SPL_MMC_BOOT
129 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
130 (uchar *)SPL_ENV_ADDR);
133 gd->env_addr = (ulong)(SPL_ENV_ADDR);
134 gd->env_valid = ENV_VALID;
140 #ifdef CONFIG_SPL_MMC_BOOT
142 #elif defined(CONFIG_SPL_NAND_BOOT)