1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2012 Freescale Semiconductor, Inc.
10 #include <asm/processor.h>
11 #include <asm/cache.h>
12 #include <asm/immap_85xx.h>
13 #include <asm/fsl_law.h>
14 #include <fsl_ddr_sdram.h>
15 #include <asm/fsl_serdes.h>
16 #include <asm/fsl_portals.h>
17 #include <asm/fsl_liodn.h>
23 #include <fsl_dtsec.h>
24 #include <asm/fsl_serdes.h>
26 #include "../common/qixis.h"
27 #include "../common/fman.h"
29 #include "t4240qds_qixis.h"
31 #define EMI_NONE 0xFFFFFFFF
40 /* Slot6 and Slot8 do not have EMI connections */
42 static int mdio_mux[NUM_FM_PORTS];
44 static const char *mdio_names[] = {
56 static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
57 static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
58 static u8 slot_qsgmii_phyaddr[5][4] = {
59 {0, 0, 0, 0},/* not used, to make index match slot No. */
65 static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0};
67 static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
69 return mdio_names[muxval];
72 struct mii_dev *mii_dev_for_muxval(u8 muxval)
75 const char *name = t4240qds_mdio_name_for_muxval(muxval);
78 printf("No bus for muxval %x\n", muxval);
82 bus = miiphy_get_dev_by_name(name);
85 printf("No bus by name %s\n", name);
92 struct t4240qds_mdio {
94 struct mii_dev *realbus;
97 static void t4240qds_mux_mdio(u8 muxval)
100 if ((muxval < 6) || (muxval == 7)) {
101 brdcfg4 = QIXIS_READ(brdcfg[4]);
102 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
103 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
104 QIXIS_WRITE(brdcfg[4], brdcfg4);
108 static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad,
111 struct t4240qds_mdio *priv = bus->priv;
113 t4240qds_mux_mdio(priv->muxval);
115 return priv->realbus->read(priv->realbus, addr, devad, regnum);
118 static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad,
119 int regnum, u16 value)
121 struct t4240qds_mdio *priv = bus->priv;
123 t4240qds_mux_mdio(priv->muxval);
125 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
128 static int t4240qds_mdio_reset(struct mii_dev *bus)
130 struct t4240qds_mdio *priv = bus->priv;
132 return priv->realbus->reset(priv->realbus);
135 static int t4240qds_mdio_init(char *realbusname, u8 muxval)
137 struct t4240qds_mdio *pmdio;
138 struct mii_dev *bus = mdio_alloc();
141 printf("Failed to allocate T4240QDS MDIO bus\n");
145 pmdio = malloc(sizeof(*pmdio));
147 printf("Failed to allocate T4240QDS private data\n");
152 bus->read = t4240qds_mdio_read;
153 bus->write = t4240qds_mdio_write;
154 bus->reset = t4240qds_mdio_reset;
155 strcpy(bus->name, t4240qds_mdio_name_for_muxval(muxval));
157 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
159 if (!pmdio->realbus) {
160 printf("No bus with name %s\n", realbusname);
166 pmdio->muxval = muxval;
169 return mdio_register(bus);
172 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
173 enum fm_port port, int offset)
175 int interface = fm_info_get_enet_if(port);
176 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
177 u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
179 prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
181 if (interface == PHY_INTERFACE_MODE_SGMII ||
182 interface == PHY_INTERFACE_MODE_QSGMII) {
185 if (qsgmiiphy_fix[port])
186 fdt_set_phy_handle(blob, prop, pa,
190 if (qsgmiiphy_fix[port])
191 fdt_set_phy_handle(blob, prop, pa,
195 if (qsgmiiphy_fix[port])
196 fdt_set_phy_handle(blob, prop, pa,
200 if (qsgmiiphy_fix[port])
201 fdt_set_phy_handle(blob, prop, pa,
205 if (qsgmiiphy_fix[port])
206 fdt_set_phy_handle(blob, prop, pa,
210 if (qsgmiiphy_fix[port])
211 fdt_set_phy_handle(blob, prop, pa,
214 fdt_set_phy_handle(blob, prop, pa,
218 if (qsgmiiphy_fix[port])
219 fdt_set_phy_handle(blob, prop, pa,
222 fdt_set_phy_handle(blob, prop, pa,
226 if (qsgmiiphy_fix[port])
227 fdt_set_phy_handle(blob, prop, pa,
231 if (qsgmiiphy_fix[port])
232 fdt_set_phy_handle(blob, prop, pa,
236 if (qsgmiiphy_fix[port])
237 fdt_set_phy_handle(blob, prop, pa,
241 if (qsgmiiphy_fix[port])
242 fdt_set_phy_handle(blob, prop, pa,
246 if (qsgmiiphy_fix[port])
247 fdt_set_phy_handle(blob, prop, pa,
251 if (qsgmiiphy_fix[port])
252 fdt_set_phy_handle(blob, prop, pa,
255 fdt_set_phy_handle(blob, prop, pa,
259 if (qsgmiiphy_fix[port])
260 fdt_set_phy_handle(blob, prop, pa,
263 fdt_set_phy_handle(blob, prop, pa,
269 } else if (interface == PHY_INTERFACE_MODE_XGMII &&
270 ((prtcl2 == 55) || (prtcl2 == 57))) {
272 * if the 10G is XFI, check hwconfig to see what is the
273 * media type, there are two types, fiber or copper,
274 * fix the dtb accordingly.
277 struct fixed_link f_link;
278 char lane_mode[20] = {"10GBASE-KR"};
279 char buf[32] = "serdes-2,";
284 if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
286 fdt_set_phy_handle(blob, prop, pa,
288 sprintf(buf, "%s%s%s", buf, "lane-a,",
293 if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
295 fdt_set_phy_handle(blob, prop, pa,
297 sprintf(buf, "%s%s%s", buf, "lane-b,",
302 if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g1")) {
304 fdt_set_phy_handle(blob, prop, pa,
306 sprintf(buf, "%s%s%s", buf, "lane-d,",
311 if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g2")) {
313 fdt_set_phy_handle(blob, prop, pa,
315 sprintf(buf, "%s%s%s", buf, "lane-c,",
324 /* fixed-link is used for XFI fiber cable */
325 fdt_delprop(blob, offset, "phy-handle");
326 f_link.phy_id = port;
328 f_link.link_speed = 10000;
330 f_link.asym_pause = 0;
331 fdt_setprop(blob, offset, "fixed-link", &f_link,
334 /* set property for copper cable */
335 off = fdt_node_offset_by_compat_reg(blob,
336 "fsl,fman-memac-mdio", pa + 0x1000);
337 fdt_setprop_string(blob, off, "lane-instance", buf);
342 void fdt_fixup_board_enet(void *fdt)
345 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
346 u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
348 prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
349 for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
350 switch (fm_info_get_enet_if(i)) {
351 case PHY_INTERFACE_MODE_SGMII:
352 case PHY_INTERFACE_MODE_QSGMII:
353 switch (mdio_mux[i]) {
355 fdt_status_okay_by_alias(fdt, "emi1_slot1");
358 fdt_status_okay_by_alias(fdt, "emi1_slot2");
361 fdt_status_okay_by_alias(fdt, "emi1_slot3");
364 fdt_status_okay_by_alias(fdt, "emi1_slot4");
370 case PHY_INTERFACE_MODE_XGMII:
371 /* check if it's XFI interface for 10g */
372 if ((prtcl2 == 55) || (prtcl2 == 57)) {
373 if (i == FM1_10GEC1 && hwconfig_sub(
374 "fsl_10gkr_copper", "fm1_10g1"))
375 fdt_status_okay_by_alias(
376 fdt, "xfi_pcs_mdio1");
377 if (i == FM1_10GEC2 && hwconfig_sub(
378 "fsl_10gkr_copper", "fm1_10g2"))
379 fdt_status_okay_by_alias(
380 fdt, "xfi_pcs_mdio2");
381 if (i == FM2_10GEC1 && hwconfig_sub(
382 "fsl_10gkr_copper", "fm2_10g1"))
383 fdt_status_okay_by_alias(
384 fdt, "xfi_pcs_mdio3");
385 if (i == FM2_10GEC2 && hwconfig_sub(
386 "fsl_10gkr_copper", "fm2_10g2"))
387 fdt_status_okay_by_alias(
388 fdt, "xfi_pcs_mdio4");
393 fdt_status_okay_by_alias(fdt, "emi2_xauislot1");
396 fdt_status_okay_by_alias(fdt, "emi2_xauislot2");
399 fdt_status_okay_by_alias(fdt, "emi2_xauislot3");
402 fdt_status_okay_by_alias(fdt, "emi2_xauislot4");
414 static void initialize_qsgmiiphy_fix(void)
419 for (i = 1; i <= 4; i++) {
421 * Try to read if a SGMII card is used, we do it slot by slot.
422 * if a SGMII PHY address is valid on a slot, then we mark
423 * all ports on the slot, then fix the PHY address for the
424 * marked port when doing dtb fixup.
426 if (miiphy_read(mdio_names[i],
427 SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, ®) != 0) {
428 debug("Slot%d PHY ID register 2 read failed\n", i);
432 debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);
435 /* No physical device present at this address */
441 qsgmiiphy_fix[FM1_DTSEC5] = 1;
442 qsgmiiphy_fix[FM1_DTSEC6] = 1;
443 qsgmiiphy_fix[FM1_DTSEC9] = 1;
444 qsgmiiphy_fix[FM1_DTSEC10] = 1;
445 slot_qsgmii_phyaddr[1][0] = SGMII_CARD_PORT1_PHY_ADDR;
446 slot_qsgmii_phyaddr[1][1] = SGMII_CARD_PORT2_PHY_ADDR;
447 slot_qsgmii_phyaddr[1][2] = SGMII_CARD_PORT3_PHY_ADDR;
448 slot_qsgmii_phyaddr[1][3] = SGMII_CARD_PORT4_PHY_ADDR;
451 qsgmiiphy_fix[FM1_DTSEC1] = 1;
452 qsgmiiphy_fix[FM1_DTSEC2] = 1;
453 qsgmiiphy_fix[FM1_DTSEC3] = 1;
454 qsgmiiphy_fix[FM1_DTSEC4] = 1;
455 slot_qsgmii_phyaddr[2][0] = SGMII_CARD_PORT1_PHY_ADDR;
456 slot_qsgmii_phyaddr[2][1] = SGMII_CARD_PORT2_PHY_ADDR;
457 slot_qsgmii_phyaddr[2][2] = SGMII_CARD_PORT3_PHY_ADDR;
458 slot_qsgmii_phyaddr[2][3] = SGMII_CARD_PORT4_PHY_ADDR;
461 qsgmiiphy_fix[FM2_DTSEC5] = 1;
462 qsgmiiphy_fix[FM2_DTSEC6] = 1;
463 qsgmiiphy_fix[FM2_DTSEC9] = 1;
464 qsgmiiphy_fix[FM2_DTSEC10] = 1;
465 slot_qsgmii_phyaddr[3][0] = SGMII_CARD_PORT1_PHY_ADDR;
466 slot_qsgmii_phyaddr[3][1] = SGMII_CARD_PORT2_PHY_ADDR;
467 slot_qsgmii_phyaddr[3][2] = SGMII_CARD_PORT3_PHY_ADDR;
468 slot_qsgmii_phyaddr[3][3] = SGMII_CARD_PORT4_PHY_ADDR;
471 qsgmiiphy_fix[FM2_DTSEC1] = 1;
472 qsgmiiphy_fix[FM2_DTSEC2] = 1;
473 qsgmiiphy_fix[FM2_DTSEC3] = 1;
474 qsgmiiphy_fix[FM2_DTSEC4] = 1;
475 slot_qsgmii_phyaddr[4][0] = SGMII_CARD_PORT1_PHY_ADDR;
476 slot_qsgmii_phyaddr[4][1] = SGMII_CARD_PORT2_PHY_ADDR;
477 slot_qsgmii_phyaddr[4][2] = SGMII_CARD_PORT3_PHY_ADDR;
478 slot_qsgmii_phyaddr[4][3] = SGMII_CARD_PORT4_PHY_ADDR;
486 int board_eth_init(bd_t *bis)
488 #if defined(CONFIG_FMAN_ENET)
489 int i, idx, lane, slot, interface;
490 struct memac_mdio_info dtsec_mdio_info;
491 struct memac_mdio_info tgec_mdio_info;
492 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
493 u32 srds_prtcl_s1, srds_prtcl_s2;
495 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
496 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
497 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
498 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
499 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
500 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
502 /* Initialize the mdio_mux array so we can recognize empty elements */
503 for (i = 0; i < NUM_FM_PORTS; i++)
504 mdio_mux[i] = EMI_NONE;
506 dtsec_mdio_info.regs =
507 (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
509 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
511 /* Register the 1G MDIO bus */
512 fm_memac_mdio_init(bis, &dtsec_mdio_info);
514 tgec_mdio_info.regs =
515 (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
516 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
518 /* Register the 10G MDIO bus */
519 fm_memac_mdio_init(bis, &tgec_mdio_info);
521 /* Register the muxing front-ends to the MDIO buses */
522 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
523 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
524 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
525 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
526 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
527 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
528 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
529 t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
531 initialize_qsgmiiphy_fix();
533 switch (srds_prtcl_s1) {
537 /* XAUI/HiGig in Slot1 and Slot2 */
538 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
539 fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
545 /* SGMII in Slot1 and Slot2 */
546 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
547 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
548 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
549 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
550 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
551 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
552 if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
553 fm_info_set_phy_address(FM1_DTSEC9,
554 slot_qsgmii_phyaddr[1][3]);
555 fm_info_set_phy_address(FM1_DTSEC10,
556 slot_qsgmii_phyaddr[1][2]);
561 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
562 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
563 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
564 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
565 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
566 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
567 if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
568 fm_info_set_phy_address(FM1_DTSEC9,
569 slot_qsgmii_phyaddr[1][2]);
570 fm_info_set_phy_address(FM1_DTSEC10,
571 slot_qsgmii_phyaddr[1][3]);
580 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
581 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
582 if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
583 fm_info_set_phy_address(FM1_DTSEC10,
584 slot_qsgmii_phyaddr[1][2]);
585 fm_info_set_phy_address(FM1_DTSEC9,
586 slot_qsgmii_phyaddr[1][3]);
588 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
589 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
590 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
591 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
594 puts("Invalid SerDes1 protocol for T4240QDS\n");
598 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
599 idx = i - FM1_DTSEC1;
600 interface = fm_info_get_enet_if(i);
602 case PHY_INTERFACE_MODE_SGMII:
603 case PHY_INTERFACE_MODE_QSGMII:
604 if (interface == PHY_INTERFACE_MODE_QSGMII) {
606 lane = serdes_get_first_lane(FSL_SRDS_1,
609 lane = serdes_get_first_lane(FSL_SRDS_1,
613 slot = lane_to_slot_fsm1[lane];
614 debug("FM1@DTSEC%u expects QSGMII in slot %u\n",
617 lane = serdes_get_first_lane(FSL_SRDS_1,
618 SGMII_FM1_DTSEC1 + idx);
621 slot = lane_to_slot_fsm1[lane];
622 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
625 if (QIXIS_READ(present2) & (1 << (slot - 1)))
629 mdio_mux[i] = EMI1_SLOT1;
631 mii_dev_for_muxval(mdio_mux[i]));
634 mdio_mux[i] = EMI1_SLOT2;
636 mii_dev_for_muxval(mdio_mux[i]));
640 case PHY_INTERFACE_MODE_RGMII:
641 /* FM1 DTSEC5 routes to RGMII with EC2 */
642 debug("FM1@DTSEC%u is RGMII at address %u\n",
645 fm_info_set_phy_address(i, 2);
646 mdio_mux[i] = EMI1_RGMII;
648 mii_dev_for_muxval(mdio_mux[i]));
655 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
656 idx = i - FM1_10GEC1;
657 switch (fm_info_get_enet_if(i)) {
658 case PHY_INTERFACE_MODE_XGMII:
659 if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
660 /* A fake PHY address to make U-Boot happy */
661 fm_info_set_phy_address(i, i);
663 lane = serdes_get_first_lane(FSL_SRDS_1,
664 XAUI_FM1_MAC9 + idx);
667 slot = lane_to_slot_fsm1[lane];
668 if (QIXIS_READ(present2) & (1 << (slot - 1)))
672 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
679 #if (CONFIG_SYS_NUM_FMAN == 2)
680 switch (srds_prtcl_s2) {
684 /* XAUI/HiGig in Slot3 and Slot4 */
685 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
686 fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
701 /* XAUI/HiGig in Slot3, SGMII in Slot4 */
702 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
703 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
704 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
705 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
706 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
712 /* SGMII in Slot3 and Slot4 */
713 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
714 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
715 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
716 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
717 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
718 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
719 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
720 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
724 /* QSGMII in Slot3 and Slot4 */
725 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
726 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
727 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
728 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
729 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
730 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
731 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]);
732 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]);
741 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
742 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
743 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
744 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
745 /* QSGMII in Slot4 */
746 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
747 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
748 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
749 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
757 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
758 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
759 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
760 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
761 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
765 /* XFI in Slot3, SGMII in Slot4 */
766 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
767 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
768 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
769 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
772 puts("Invalid SerDes2 protocol for T4240QDS\n");
776 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
777 idx = i - FM2_DTSEC1;
778 interface = fm_info_get_enet_if(i);
780 case PHY_INTERFACE_MODE_SGMII:
781 case PHY_INTERFACE_MODE_QSGMII:
782 if (interface == PHY_INTERFACE_MODE_QSGMII) {
784 lane = serdes_get_first_lane(FSL_SRDS_2,
787 lane = serdes_get_first_lane(FSL_SRDS_2,
791 slot = lane_to_slot_fsm2[lane];
792 debug("FM2@DTSEC%u expects QSGMII in slot %u\n",
795 lane = serdes_get_first_lane(FSL_SRDS_2,
796 SGMII_FM2_DTSEC1 + idx);
799 slot = lane_to_slot_fsm2[lane];
800 debug("FM2@DTSEC%u expects SGMII in slot %u\n",
803 if (QIXIS_READ(present2) & (1 << (slot - 1)))
807 mdio_mux[i] = EMI1_SLOT3;
809 mii_dev_for_muxval(mdio_mux[i]));
812 mdio_mux[i] = EMI1_SLOT4;
814 mii_dev_for_muxval(mdio_mux[i]));
818 case PHY_INTERFACE_MODE_RGMII:
820 * If DTSEC5 is RGMII, then it's routed via via EC1 to
821 * the first on-board RGMII port. If DTSEC6 is RGMII,
822 * then it's routed via via EC2 to the second on-board
825 debug("FM2@DTSEC%u is RGMII at address %u\n",
826 idx + 1, i == FM2_DTSEC5 ? 1 : 2);
827 fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
828 mdio_mux[i] = EMI1_RGMII;
829 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
836 for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
837 idx = i - FM2_10GEC1;
838 switch (fm_info_get_enet_if(i)) {
839 case PHY_INTERFACE_MODE_XGMII:
840 if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
841 /* A fake PHY address to make U-Boot happy */
842 fm_info_set_phy_address(i, i);
844 lane = serdes_get_first_lane(FSL_SRDS_2,
845 XAUI_FM2_MAC9 + idx);
848 slot = lane_to_slot_fsm2[lane];
849 if (QIXIS_READ(present2) & (1 << (slot - 1)))
853 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
859 #endif /* CONFIG_SYS_NUM_FMAN */
862 #endif /* CONFIG_FMAN_ENET */
864 return pci_eth_init(bis);