board/freescale/t4qds/ddr.c

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <hwconfig.h>
  10 #include <asm/mmu.h>
  11 #include <fsl_ddr_sdram.h>
  12 #include <fsl_ddr_dimm_params.h>
  13 #include <asm/fsl_law.h>
  14 #include "ddr.h"
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 void fsl_ddr_board_options(memctl_options_t *popts,
  19                                 dimm_params_t *pdimm,
  20                                 unsigned int ctrl_num)
  21 {
  22         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  23         ulong ddr_freq;
  24
  25         if (ctrl_num > 2) {
  26                 printf("Not supported controller number %d\n", ctrl_num);
  27                 return;
  28         }
  29         if (!pdimm->n_ranks)
  30                 return;
  31
  32         /*
  33          * we use identical timing for all slots. If needed, change the code
  34          * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
  35          */
  36         if (popts->registered_dimm_en)
  37                 pbsp = rdimms[0];
  38         else
  39                 pbsp = udimms[0];
  40
  41
  42         /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
  43          * freqency and n_banks specified in board_specific_parameters table.
  44          */
  45         ddr_freq = get_ddr_freq(0) / 1000000;
  46         while (pbsp->datarate_mhz_high) {
  47                 if (pbsp->n_ranks == pdimm->n_ranks &&
  48                     (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  49                         if (ddr_freq <= pbsp->datarate_mhz_high) {
  50                                 popts->cpo_override = pbsp->cpo;
  51                                 popts->write_data_delay =
  52                                         pbsp->write_data_delay;
  53                                 popts->clk_adjust = pbsp->clk_adjust;
  54                                 popts->wrlvl_start = pbsp->wrlvl_start;
  55                                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  56                                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  57                                 popts->twot_en = pbsp->force_2t;
  58                                 goto found;
  59                         }
  60                         pbsp_highest = pbsp;
  61                 }
  62                 pbsp++;
  63         }
  64
  65         if (pbsp_highest) {
  66                 printf("Error: board specific timing not found "
  67                         "for data rate %lu MT/s\n"
  68                         "Trying to use the highest speed (%u) parameters\n",
  69                         ddr_freq, pbsp_highest->datarate_mhz_high);
  70                 popts->cpo_override = pbsp_highest->cpo;
  71                 popts->write_data_delay = pbsp_highest->write_data_delay;
  72                 popts->clk_adjust = pbsp_highest->clk_adjust;
  73                 popts->wrlvl_start = pbsp_highest->wrlvl_start;
  74                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  75                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  76                 popts->twot_en = pbsp_highest->force_2t;
  77         } else {
  78                 panic("DIMM is not supported by this board");
  79         }
  80 found:
  81         debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  82                 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
  83                 "wrlvl_ctrl_3 0x%x\n",
  84                 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  85                 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  86                 pbsp->wrlvl_ctl_3);
  87
  88         /*
  89          * Factors to consider for half-strength driver enable:
  90          *      - number of DIMMs installed
  91          */
  92         popts->half_strength_driver_enable = 0;
  93         /*
  94          * Write leveling override
  95          */
  96         popts->wrlvl_override = 1;
  97         popts->wrlvl_sample = 0xf;
  98
  99         /*
 100          * Rtt and Rtt_WR override
 101          */
 102         popts->rtt_override = 0;
 103
 104         /* Enable ZQ calibration */
 105         popts->zq_en = 1;
 106
 107         /* DHC_EN =1, ODT = 75 Ohm */
 108         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 109         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
 110
 111         /* optimize cpo for erratum A-009942 */
 112         popts->cpo_sample = 0x63;
 113 }
 114
 115 int dram_init(void)
 116 {
 117         phys_size_t dram_size;
 118
 119         puts("Initializing....using SPD\n");
 120
 121 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 122         dram_size = fsl_ddr_sdram();
 123 #else
 124         /* DDR has been initialised by first stage boot loader */
 125         dram_size = fsl_ddr_sdram_size();
 126 #endif
 127         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 128         dram_size *= 0x100000;
 129
 130         gd->ram_size = dram_size;
 131
 132         return 0;
 133 }