board/freescale/t208xrdb/eth_t208xrdb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  *
   5  * Shengzhou Liu <Shengzhou.Liu@freescale.com>
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <netdev.h>
  11 #include <asm/mmu.h>
  12 #include <asm/processor.h>
  13 #include <asm/immap_85xx.h>
  14 #include <asm/fsl_law.h>
  15 #include <asm/fsl_serdes.h>
  16 #include <asm/fsl_portals.h>
  17 #include <asm/fsl_liodn.h>
  18 #include <malloc.h>
  19 #include <fm_eth.h>
  20 #include <fsl_mdio.h>
  21 #include <miiphy.h>
  22 #include <phy.h>
  23 #include <fsl_dtsec.h>
  24 #include <asm/fsl_serdes.h>
  25
  26 int board_eth_init(bd_t *bis)
  27 {
  28 #if defined(CONFIG_FMAN_ENET)
  29         int i, interface;
  30         struct memac_mdio_info dtsec_mdio_info;
  31         struct memac_mdio_info tgec_mdio_info;
  32         struct mii_dev *dev;
  33         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  34         u32 srds_s1;
  35
  36         srds_s1 = in_be32(&gur->rcwsr[4]) &
  37                                         FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  38         srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  39
  40         dtsec_mdio_info.regs =
  41                 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
  42
  43         dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  44
  45         /* Register the 1G MDIO bus */
  46         fm_memac_mdio_init(bis, &dtsec_mdio_info);
  47
  48         tgec_mdio_info.regs =
  49                 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
  50         tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  51
  52         /* Register the 10G MDIO bus */
  53         fm_memac_mdio_init(bis, &tgec_mdio_info);
  54
  55         /* Set the two on-board RGMII PHY address */
  56         fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
  57         fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
  58
  59         switch (srds_s1) {
  60         case 0x66:
  61         case 0x6b:
  62                 fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1);
  63                 fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2);
  64                 fm_info_set_phy_address(FM1_10GEC3, FM1_10GEC3_PHY_ADDR);
  65                 fm_info_set_phy_address(FM1_10GEC4, FM1_10GEC4_PHY_ADDR);
  66                 break;
  67         default:
  68                 printf("SerDes1 protocol 0x%x is not supported on T208xRDB\n",
  69                        srds_s1);
  70                 break;
  71         }
  72
  73         for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  74                 interface = fm_info_get_enet_if(i);
  75                 switch (interface) {
  76                 case PHY_INTERFACE_MODE_RGMII:
  77                         dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
  78                         fm_info_set_mdio(i, dev);
  79                         break;
  80                 default:
  81                         break;
  82                 }
  83         }
  84
  85         for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
  86                 switch (fm_info_get_enet_if(i)) {
  87                 case PHY_INTERFACE_MODE_XGMII:
  88                         dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
  89                         fm_info_set_mdio(i, dev);
  90                         break;
  91                 default:
  92                         break;
  93                 }
  94         }
  95
  96         cpu_eth_init(bis);
  97 #endif /* CONFIG_FMAN_ENET */
  98
  99         return pci_eth_init(bis);
 100 }
 101
 102 void fdt_fixup_board_enet(void *fdt)
 103 {
 104         return;
 105 }