board/freescale/t208xqds/t208xqds.c

   1 /*
   2  * Copyright 2009-2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <i2c.h>
  10 #include <netdev.h>
  11 #include <linux/compiler.h>
  12 #include <asm/mmu.h>
  13 #include <asm/processor.h>
  14 #include <asm/immap_85xx.h>
  15 #include <asm/fsl_law.h>
  16 #include <asm/fsl_serdes.h>
  17 #include <asm/fsl_liodn.h>
  18 #include <fm_eth.h>
  19
  20 #include "../common/qixis.h"
  21 #include "../common/vsc3316_3308.h"
  22 #include "../common/vid.h"
  23 #include "t208xqds.h"
  24 #include "t208xqds_qixis.h"
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 int checkboard(void)
  29 {
  30         char buf[64];
  31         u8 sw;
  32         struct cpu_type *cpu = gd->arch.cpu;
  33         static const char *freq[4] = {
  34                 "100.00MHZ(from 8T49N222A)", "125.00MHz",
  35                 "156.25MHZ", "100.00MHz"
  36         };
  37
  38         printf("Board: %sQDS, ", cpu->name);
  39         sw = QIXIS_READ(arch);
  40         printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
  41         printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  42
  43 #ifdef CONFIG_SDCARD
  44         puts("SD/MMC\n");
  45 #elif CONFIG_SPIFLASH
  46         puts("SPI\n");
  47 #else
  48         sw = QIXIS_READ(brdcfg[0]);
  49         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  50
  51         if (sw < 0x8)
  52                 printf("vBank%d\n", sw);
  53         else if (sw == 0x8)
  54                 puts("Promjet\n");
  55         else if (sw == 0x9)
  56                 puts("NAND\n");
  57         else
  58                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  59 #endif
  60
  61         printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
  62                qixis_read_tag(buf), (int)qixis_read_minor());
  63         /* the timestamp string contains "\n" at the end */
  64         printf(" on %s", qixis_read_time(buf));
  65
  66         puts("SERDES Reference Clocks:\n");
  67         sw = QIXIS_READ(brdcfg[2]);
  68         printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
  69                freq[(sw >> 4) & 0x3]);
  70         printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
  71                freq[sw & 0x3]);
  72
  73         return 0;
  74 }
  75
  76 int select_i2c_ch_pca9547(u8 ch)
  77 {
  78         int ret;
  79
  80         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  81         if (ret) {
  82                 puts("PCA: failed to select proper channel\n");
  83                 return ret;
  84         }
  85
  86         return 0;
  87 }
  88
  89 int i2c_multiplexer_select_vid_channel(u8 channel)
  90 {
  91         return select_i2c_ch_pca9547(channel);
  92 }
  93
  94 int brd_mux_lane_to_slot(void)
  95 {
  96         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  97         u32 srds_prtcl_s1;
  98
  99         srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
 100                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 101         srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 102 #if defined(CONFIG_TARGET_T2080QDS)
 103         u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
 104                                 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 105         srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 106 #endif
 107
 108         switch (srds_prtcl_s1) {
 109         case 0:
 110                 /* SerDes1 is not enabled */
 111                 break;
 112 #if defined(CONFIG_TARGET_T2080QDS)
 113         case 0x1b:
 114         case 0x1c:
 115         case 0xa2:
 116                 /* SD1(A:D) => SLOT3 SGMII
 117                  * SD1(G:H) => SLOT1 SGMII
 118                  */
 119                 QIXIS_WRITE(brdcfg[12], 0x1a);
 120                 break;
 121         case 0x94:
 122         case 0x95:
 123                 /* SD1(A:B) => SLOT3 SGMII@1.25bps
 124                  * SD1(C:D) => SFP Module, SGMII@3.125bps
 125                  * SD1(E:H) => SLOT1 SGMII@1.25bps
 126                  */
 127         case 0x96:
 128                 /* SD1(A:B) => SLOT3 SGMII@1.25bps
 129                  * SD1(C)   => SFP Module, SGMII@3.125bps
 130                  * SD1(D)   => SFP Module, SGMII@1.25bps
 131                  * SD1(E:H) => SLOT1 PCIe4 x4
 132                  */
 133                 QIXIS_WRITE(brdcfg[12], 0x3a);
 134                 break;
 135         case 0x50:
 136         case 0x51:
 137                 /* SD1(A:D) => SLOT3 XAUI
 138                  * SD1(E)   => SLOT1 PCIe4
 139                  * SD1(F:H) => SLOT2 SGMII
 140                  */
 141                 QIXIS_WRITE(brdcfg[12], 0x15);
 142                 break;
 143         case 0x66:
 144         case 0x67:
 145                 /* SD1(A:D) => XFI cage
 146                  * SD1(E:H) => SLOT1 PCIe4
 147                  */
 148                 QIXIS_WRITE(brdcfg[12], 0xfe);
 149                 break;
 150         case 0x6a:
 151         case 0x6b:
 152                 /* SD1(A:D) => XFI cage
 153                  * SD1(E)   => SLOT1 PCIe4
 154                  * SD1(F:H) => SLOT2 SGMII
 155                  */
 156                 QIXIS_WRITE(brdcfg[12], 0xf1);
 157                 break;
 158         case 0x6c:
 159         case 0x6d:
 160                 /* SD1(A:B) => XFI cage
 161                  * SD1(C:D) => SLOT3 SGMII
 162                  * SD1(E:H) => SLOT1 PCIe4
 163                  */
 164                 QIXIS_WRITE(brdcfg[12], 0xda);
 165                 break;
 166         case 0x6e:
 167                 /* SD1(A:B) => SFP Module, XFI
 168                  * SD1(C:D) => SLOT3 SGMII
 169                  * SD1(E:F) => SLOT1 PCIe4 x2
 170                  * SD1(G:H) => SLOT2 SGMII
 171                  */
 172                 QIXIS_WRITE(brdcfg[12], 0xd9);
 173                 break;
 174         case 0xda:
 175                 /* SD1(A:H) => SLOT3 PCIe3 x8
 176                  */
 177                  QIXIS_WRITE(brdcfg[12], 0x0);
 178                  break;
 179         case 0xc8:
 180                 /* SD1(A)   => SLOT3 PCIe3 x1
 181                  * SD1(B)   => SFP Module, SGMII@1.25bps
 182                  * SD1(C:D) => SFP Module, SGMII@3.125bps
 183                  * SD1(E:F) => SLOT1 PCIe4 x2
 184                  * SD1(G:H) => SLOT2 SGMII
 185                  */
 186                  QIXIS_WRITE(brdcfg[12], 0x79);
 187                  break;
 188         case 0xab:
 189                 /* SD1(A:D) => SLOT3 PCIe3 x4
 190                  * SD1(E:H) => SLOT1 PCIe4 x4
 191                  */
 192                  QIXIS_WRITE(brdcfg[12], 0x1a);
 193                  break;
 194 #elif defined(CONFIG_TARGET_T2081QDS)
 195         case 0x50:
 196         case 0x51:
 197                 /* SD1(A:D) => SLOT2 XAUI
 198                  * SD1(E)   => SLOT1 PCIe4 x1
 199                  * SD1(F:H) => SLOT3 SGMII
 200                  */
 201                 QIXIS_WRITE(brdcfg[12], 0x98);
 202                 QIXIS_WRITE(brdcfg[13], 0x70);
 203                 break;
 204         case 0x6a:
 205         case 0x6b:
 206                 /* SD1(A:D) => XFI SFP Module
 207                  * SD1(E)   => SLOT1 PCIe4 x1
 208                  * SD1(F:H) => SLOT3 SGMII
 209                  */
 210                 QIXIS_WRITE(brdcfg[12], 0x80);
 211                 QIXIS_WRITE(brdcfg[13], 0x70);
 212                 break;
 213         case 0x6c:
 214         case 0x6d:
 215                 /* SD1(A:B) => XFI SFP Module
 216                  * SD1(C:D) => SLOT2 SGMII
 217                  * SD1(E:H) => SLOT1 PCIe4 x4
 218                  */
 219                 QIXIS_WRITE(brdcfg[12], 0xe8);
 220                 QIXIS_WRITE(brdcfg[13], 0x0);
 221                 break;
 222         case 0xaa:
 223         case 0xab:
 224                 /* SD1(A:D) => SLOT2 PCIe3 x4
 225                  * SD1(F:H) => SLOT1 SGMI4 x4
 226                  */
 227                 QIXIS_WRITE(brdcfg[12], 0xf8);
 228                 QIXIS_WRITE(brdcfg[13], 0x0);
 229                 break;
 230         case 0xca:
 231         case 0xcb:
 232                 /* SD1(A)   => SLOT2 PCIe3 x1
 233                  * SD1(B)   => SLOT7 SGMII
 234                  * SD1(C)   => SLOT6 SGMII
 235                  * SD1(D)   => SLOT5 SGMII
 236                  * SD1(E)   => SLOT1 PCIe4 x1
 237                  * SD1(F:H) => SLOT3 SGMII
 238                  */
 239                 QIXIS_WRITE(brdcfg[12], 0x80);
 240                 QIXIS_WRITE(brdcfg[13], 0x70);
 241                 break;
 242         case 0xde:
 243         case 0xdf:
 244                 /* SD1(A:D) => SLOT2 PCIe3 x4
 245                  * SD1(E)   => SLOT1 PCIe4 x1
 246                  * SD1(F)   => SLOT4 PCIe1 x1
 247                  * SD1(G)   => SLOT3 PCIe2 x1
 248                  * SD1(H)   => SLOT7 SGMII
 249                  */
 250                 QIXIS_WRITE(brdcfg[12], 0x98);
 251                 QIXIS_WRITE(brdcfg[13], 0x25);
 252                 break;
 253         case 0xf2:
 254                 /* SD1(A)   => SLOT2 PCIe3 x1
 255                  * SD1(B:D) => SLOT7 SGMII
 256                  * SD1(E)   => SLOT1 PCIe4 x1
 257                  * SD1(F)   => SLOT4 PCIe1 x1
 258                  * SD1(G)   => SLOT3 PCIe2 x1
 259                  * SD1(H)   => SLOT7 SGMII
 260                  */
 261                 QIXIS_WRITE(brdcfg[12], 0x81);
 262                 QIXIS_WRITE(brdcfg[13], 0xa5);
 263                 break;
 264 #endif
 265         default:
 266                 printf("WARNING: unsupported for SerDes1 Protocol %d\n",
 267                        srds_prtcl_s1);
 268                 return -1;
 269         }
 270
 271 #ifdef CONFIG_TARGET_T2080QDS
 272         switch (srds_prtcl_s2) {
 273         case 0:
 274                 /* SerDes2 is not enabled */
 275                 break;
 276         case 0x01:
 277         case 0x02:
 278                 /* SD2(A:H) => SLOT4 PCIe1 */
 279                 QIXIS_WRITE(brdcfg[13], 0x10);
 280                 break;
 281         case 0x15:
 282         case 0x16:
 283                 /*
 284                  * SD2(A:D) => SLOT4 PCIe1
 285                  * SD2(E:F) => SLOT5 PCIe2
 286                  * SD2(G:H) => SATA1,SATA2
 287                  */
 288                 QIXIS_WRITE(brdcfg[13], 0xb0);
 289                 break;
 290         case 0x18:
 291                 /*
 292                  * SD2(A:D) => SLOT4 PCIe1
 293                  * SD2(E:F) => SLOT5 Aurora
 294                  * SD2(G:H) => SATA1,SATA2
 295                  */
 296                 QIXIS_WRITE(brdcfg[13], 0x78);
 297                 break;
 298         case 0x1f:
 299                 /*
 300                  * SD2(A:D) => SLOT4 PCIe1
 301                  * SD2(E:H) => SLOT5 PCIe2
 302                  */
 303                 QIXIS_WRITE(brdcfg[13], 0xa0);
 304                 break;
 305         case 0x29:
 306         case 0x2d:
 307         case 0x2e:
 308                 /*
 309                  * SD2(A:D) => SLOT4 SRIO2
 310                  * SD2(E:H) => SLOT5 SRIO1
 311                  */
 312                 QIXIS_WRITE(brdcfg[13], 0xa0);
 313                 break;
 314         case 0x36:
 315                 /*
 316                  * SD2(A:D) => SLOT4 SRIO2
 317                  * SD2(E:F) => Aurora
 318                  * SD2(G:H) => SATA1,SATA2
 319                  */
 320                 QIXIS_WRITE(brdcfg[13], 0x78);
 321                 break;
 322         default:
 323                 printf("WARNING: unsupported for SerDes2 Protocol %d\n",
 324                        srds_prtcl_s2);
 325                 return -1;
 326         }
 327 #endif
 328         return 0;
 329 }
 330
 331 int board_early_init_r(void)
 332 {
 333         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 334         int flash_esel = find_tlb_idx((void *)flashbase, 1);
 335
 336         /*
 337          * Remap Boot flash + PROMJET region to caching-inhibited
 338          * so that flash can be erased properly.
 339          */
 340
 341         /* Flush d-cache and invalidate i-cache of any FLASH data */
 342         flush_dcache();
 343         invalidate_icache();
 344
 345         if (flash_esel == -1) {
 346                 /* very unlikely unless something is messed up */
 347                 puts("Error: Could not find TLB for FLASH BASE\n");
 348                 flash_esel = 2; /* give our best effort to continue */
 349         } else {
 350                 /* invalidate existing TLB entry for flash + promjet */
 351                 disable_tlb(flash_esel);
 352         }
 353
 354         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 355                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 356                 0, flash_esel, BOOKE_PAGESZ_256M, 1);
 357
 358         /* Disable remote I2C connection to qixis fpga */
 359         QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
 360
 361         /*
 362          * Adjust core voltage according to voltage ID
 363          * This function changes I2C mux to channel 2.
 364          */
 365         if (adjust_vdd(0))
 366                 printf("Warning: Adjusting core voltage failed.\n");
 367
 368         brd_mux_lane_to_slot();
 369         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 370
 371         return 0;
 372 }
 373
 374 unsigned long get_board_sys_clk(void)
 375 {
 376         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 377 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
 378         /* use accurate clock measurement */
 379         int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
 380         int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
 381         u32 val;
 382
 383         val =  freq * base;
 384         if (val) {
 385                 debug("SYS Clock measurement is: %d\n", val);
 386                 return val;
 387         } else {
 388                 printf("Warning: SYS clock measurement is invalid, ");
 389                 printf("using value from brdcfg1.\n");
 390         }
 391 #endif
 392
 393         switch (sysclk_conf & 0x0F) {
 394         case QIXIS_SYSCLK_83:
 395                 return 83333333;
 396         case QIXIS_SYSCLK_100:
 397                 return 100000000;
 398         case QIXIS_SYSCLK_125:
 399                 return 125000000;
 400         case QIXIS_SYSCLK_133:
 401                 return 133333333;
 402         case QIXIS_SYSCLK_150:
 403                 return 150000000;
 404         case QIXIS_SYSCLK_160:
 405                 return 160000000;
 406         case QIXIS_SYSCLK_166:
 407                 return 166666666;
 408         }
 409         return 66666666;
 410 }
 411
 412 unsigned long get_board_ddr_clk(void)
 413 {
 414         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 415 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
 416         /* use accurate clock measurement */
 417         int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
 418         int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
 419         u32 val;
 420
 421         val =  freq * base;
 422         if (val) {
 423                 debug("DDR Clock measurement is: %d\n", val);
 424                 return val;
 425         } else {
 426                 printf("Warning: DDR clock measurement is invalid, ");
 427                 printf("using value from brdcfg1.\n");
 428         }
 429 #endif
 430
 431         switch ((ddrclk_conf & 0x30) >> 4) {
 432         case QIXIS_DDRCLK_100:
 433                 return 100000000;
 434         case QIXIS_DDRCLK_125:
 435                 return 125000000;
 436         case QIXIS_DDRCLK_133:
 437                 return 133333333;
 438         }
 439         return 66666666;
 440 }
 441
 442 int misc_init_r(void)
 443 {
 444         return 0;
 445 }
 446
 447 int ft_board_setup(void *blob, bd_t *bd)
 448 {
 449         phys_addr_t base;
 450         phys_size_t size;
 451
 452         ft_cpu_setup(blob, bd);
 453
 454         base = env_get_bootm_low();
 455         size = env_get_bootm_size();
 456
 457         fdt_fixup_memory(blob, (u64)base, (u64)size);
 458
 459 #ifdef CONFIG_PCI
 460         pci_of_setup(blob, bd);
 461 #endif
 462
 463         fdt_fixup_liodn(blob);
 464         fsl_fdt_fixup_dr_usb(blob, bd);
 465
 466 #ifdef CONFIG_SYS_DPAA_FMAN
 467         fdt_fixup_fman_ethernet(blob);
 468         fdt_fixup_board_enet(blob);
 469 #endif
 470
 471         return 0;
 472 }