board/freescale/t208xqds/t208xqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2009-2013 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <env.h>
  10 #include <fdt_support.h>
  11 #include <i2c.h>
  12 #include <init.h>
  13 #include <netdev.h>
  14 #include <linux/compiler.h>
  15 #include <asm/mmu.h>
  16 #include <asm/processor.h>
  17 #include <asm/immap_85xx.h>
  18 #include <asm/fsl_law.h>
  19 #include <asm/fsl_serdes.h>
  20 #include <asm/fsl_liodn.h>
  21 #include <fm_eth.h>
  22
  23 #include "../common/qixis.h"
  24 #include "../common/vsc3316_3308.h"
  25 #include "../common/vid.h"
  26 #include "t208xqds.h"
  27 #include "t208xqds_qixis.h"
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 int checkboard(void)
  32 {
  33         char buf[64];
  34         u8 sw;
  35         struct cpu_type *cpu = gd->arch.cpu;
  36         static const char *freq[4] = {
  37                 "100.00MHZ(from 8T49N222A)", "125.00MHz",
  38                 "156.25MHZ", "100.00MHz"
  39         };
  40
  41         printf("Board: %sQDS, ", cpu->name);
  42         sw = QIXIS_READ(arch);
  43         printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
  44         printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  45
  46 #ifdef CONFIG_SDCARD
  47         puts("SD/MMC\n");
  48 #elif CONFIG_SPIFLASH
  49         puts("SPI\n");
  50 #else
  51         sw = QIXIS_READ(brdcfg[0]);
  52         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  53
  54         if (sw < 0x8)
  55                 printf("vBank%d\n", sw);
  56         else if (sw == 0x8)
  57                 puts("Promjet\n");
  58         else if (sw == 0x9)
  59                 puts("NAND\n");
  60         else
  61                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  62 #endif
  63
  64         printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
  65                qixis_read_tag(buf), (int)qixis_read_minor());
  66         /* the timestamp string contains "\n" at the end */
  67         printf(" on %s", qixis_read_time(buf));
  68
  69         puts("SERDES Reference Clocks:\n");
  70         sw = QIXIS_READ(brdcfg[2]);
  71         printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
  72                freq[(sw >> 4) & 0x3]);
  73         printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
  74                freq[sw & 0x3]);
  75
  76         return 0;
  77 }
  78
  79 int select_i2c_ch_pca9547(u8 ch, int bus_num)
  80 {
  81         int ret;
  82
  83 #ifdef CONFIG_DM_I2C
  84         struct udevice *dev;
  85
  86         ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  87         if (ret) {
  88                 printf("%s: Cannot find udev for a bus %d\n", __func__,
  89                        bus_num);
  90                 return ret;
  91         }
  92         ret = dm_i2c_write(dev, 0, &ch, 1);
  93 #else
  94         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  95 #endif
  96         if (ret) {
  97                 puts("PCA: failed to select proper channel\n");
  98                 return ret;
  99         }
 100
 101         return 0;
 102 }
 103
 104 int i2c_multiplexer_select_vid_channel(u8 channel)
 105 {
 106         return select_i2c_ch_pca9547(channel, 0);
 107 }
 108
 109 int brd_mux_lane_to_slot(void)
 110 {
 111         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 112         u32 srds_prtcl_s1;
 113
 114         srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
 115                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 116         srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 117 #if defined(CONFIG_TARGET_T2080QDS)
 118         u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
 119                                 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 120         srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 121 #endif
 122
 123         switch (srds_prtcl_s1) {
 124         case 0:
 125                 /* SerDes1 is not enabled */
 126                 break;
 127 #if defined(CONFIG_TARGET_T2080QDS)
 128         case 0x1b:
 129         case 0x1c:
 130         case 0xa2:
 131                 /* SD1(A:D) => SLOT3 SGMII
 132                  * SD1(G:H) => SLOT1 SGMII
 133                  */
 134                 QIXIS_WRITE(brdcfg[12], 0x1a);
 135                 break;
 136         case 0x94:
 137         case 0x95:
 138                 /* SD1(A:B) => SLOT3 SGMII@1.25bps
 139                  * SD1(C:D) => SFP Module, SGMII@3.125bps
 140                  * SD1(E:H) => SLOT1 SGMII@1.25bps
 141                  */
 142         case 0x96:
 143                 /* SD1(A:B) => SLOT3 SGMII@1.25bps
 144                  * SD1(C)   => SFP Module, SGMII@3.125bps
 145                  * SD1(D)   => SFP Module, SGMII@1.25bps
 146                  * SD1(E:H) => SLOT1 PCIe4 x4
 147                  */
 148                 QIXIS_WRITE(brdcfg[12], 0x3a);
 149                 break;
 150         case 0x50:
 151         case 0x51:
 152                 /* SD1(A:D) => SLOT3 XAUI
 153                  * SD1(E)   => SLOT1 PCIe4
 154                  * SD1(F:H) => SLOT2 SGMII
 155                  */
 156                 QIXIS_WRITE(brdcfg[12], 0x15);
 157                 break;
 158         case 0x66:
 159         case 0x67:
 160                 /* SD1(A:D) => XFI cage
 161                  * SD1(E:H) => SLOT1 PCIe4
 162                  */
 163                 QIXIS_WRITE(brdcfg[12], 0xfe);
 164                 break;
 165         case 0x6a:
 166         case 0x6b:
 167                 /* SD1(A:D) => XFI cage
 168                  * SD1(E)   => SLOT1 PCIe4
 169                  * SD1(F:H) => SLOT2 SGMII
 170                  */
 171                 QIXIS_WRITE(brdcfg[12], 0xf1);
 172                 break;
 173         case 0x6c:
 174         case 0x6d:
 175                 /* SD1(A:B) => XFI cage
 176                  * SD1(C:D) => SLOT3 SGMII
 177                  * SD1(E:H) => SLOT1 PCIe4
 178                  */
 179                 QIXIS_WRITE(brdcfg[12], 0xda);
 180                 break;
 181         case 0x6e:
 182                 /* SD1(A:B) => SFP Module, XFI
 183                  * SD1(C:D) => SLOT3 SGMII
 184                  * SD1(E:F) => SLOT1 PCIe4 x2
 185                  * SD1(G:H) => SLOT2 SGMII
 186                  */
 187                 QIXIS_WRITE(brdcfg[12], 0xd9);
 188                 break;
 189         case 0xda:
 190                 /* SD1(A:H) => SLOT3 PCIe3 x8
 191                  */
 192                  QIXIS_WRITE(brdcfg[12], 0x0);
 193                  break;
 194         case 0xc8:
 195                 /* SD1(A)   => SLOT3 PCIe3 x1
 196                  * SD1(B)   => SFP Module, SGMII@1.25bps
 197                  * SD1(C:D) => SFP Module, SGMII@3.125bps
 198                  * SD1(E:F) => SLOT1 PCIe4 x2
 199                  * SD1(G:H) => SLOT2 SGMII
 200                  */
 201                  QIXIS_WRITE(brdcfg[12], 0x79);
 202                  break;
 203         case 0xab:
 204                 /* SD1(A:D) => SLOT3 PCIe3 x4
 205                  * SD1(E:H) => SLOT1 PCIe4 x4
 206                  */
 207                  QIXIS_WRITE(brdcfg[12], 0x1a);
 208                  break;
 209 #elif defined(CONFIG_TARGET_T2081QDS)
 210         case 0x50:
 211         case 0x51:
 212                 /* SD1(A:D) => SLOT2 XAUI
 213                  * SD1(E)   => SLOT1 PCIe4 x1
 214                  * SD1(F:H) => SLOT3 SGMII
 215                  */
 216                 QIXIS_WRITE(brdcfg[12], 0x98);
 217                 QIXIS_WRITE(brdcfg[13], 0x70);
 218                 break;
 219         case 0x6a:
 220         case 0x6b:
 221                 /* SD1(A:D) => XFI SFP Module
 222                  * SD1(E)   => SLOT1 PCIe4 x1
 223                  * SD1(F:H) => SLOT3 SGMII
 224                  */
 225                 QIXIS_WRITE(brdcfg[12], 0x80);
 226                 QIXIS_WRITE(brdcfg[13], 0x70);
 227                 break;
 228         case 0x6c:
 229         case 0x6d:
 230                 /* SD1(A:B) => XFI SFP Module
 231                  * SD1(C:D) => SLOT2 SGMII
 232                  * SD1(E:H) => SLOT1 PCIe4 x4
 233                  */
 234                 QIXIS_WRITE(brdcfg[12], 0xe8);
 235                 QIXIS_WRITE(brdcfg[13], 0x0);
 236                 break;
 237         case 0xaa:
 238         case 0xab:
 239                 /* SD1(A:D) => SLOT2 PCIe3 x4
 240                  * SD1(F:H) => SLOT1 SGMI4 x4
 241                  */
 242                 QIXIS_WRITE(brdcfg[12], 0xf8);
 243                 QIXIS_WRITE(brdcfg[13], 0x0);
 244                 break;
 245         case 0xca:
 246         case 0xcb:
 247                 /* SD1(A)   => SLOT2 PCIe3 x1
 248                  * SD1(B)   => SLOT7 SGMII
 249                  * SD1(C)   => SLOT6 SGMII
 250                  * SD1(D)   => SLOT5 SGMII
 251                  * SD1(E)   => SLOT1 PCIe4 x1
 252                  * SD1(F:H) => SLOT3 SGMII
 253                  */
 254                 QIXIS_WRITE(brdcfg[12], 0x80);
 255                 QIXIS_WRITE(brdcfg[13], 0x70);
 256                 break;
 257         case 0xde:
 258         case 0xdf:
 259                 /* SD1(A:D) => SLOT2 PCIe3 x4
 260                  * SD1(E)   => SLOT1 PCIe4 x1
 261                  * SD1(F)   => SLOT4 PCIe1 x1
 262                  * SD1(G)   => SLOT3 PCIe2 x1
 263                  * SD1(H)   => SLOT7 SGMII
 264                  */
 265                 QIXIS_WRITE(brdcfg[12], 0x98);
 266                 QIXIS_WRITE(brdcfg[13], 0x25);
 267                 break;
 268         case 0xf2:
 269                 /* SD1(A)   => SLOT2 PCIe3 x1
 270                  * SD1(B:D) => SLOT7 SGMII
 271                  * SD1(E)   => SLOT1 PCIe4 x1
 272                  * SD1(F)   => SLOT4 PCIe1 x1
 273                  * SD1(G)   => SLOT3 PCIe2 x1
 274                  * SD1(H)   => SLOT7 SGMII
 275                  */
 276                 QIXIS_WRITE(brdcfg[12], 0x81);
 277                 QIXIS_WRITE(brdcfg[13], 0xa5);
 278                 break;
 279 #endif
 280         default:
 281                 printf("WARNING: unsupported for SerDes1 Protocol %d\n",
 282                        srds_prtcl_s1);
 283                 return -1;
 284         }
 285
 286 #ifdef CONFIG_TARGET_T2080QDS
 287         switch (srds_prtcl_s2) {
 288         case 0:
 289                 /* SerDes2 is not enabled */
 290                 break;
 291         case 0x01:
 292         case 0x02:
 293                 /* SD2(A:H) => SLOT4 PCIe1 */
 294                 QIXIS_WRITE(brdcfg[13], 0x10);
 295                 break;
 296         case 0x15:
 297         case 0x16:
 298                 /*
 299                  * SD2(A:D) => SLOT4 PCIe1
 300                  * SD2(E:F) => SLOT5 PCIe2
 301                  * SD2(G:H) => SATA1,SATA2
 302                  */
 303                 QIXIS_WRITE(brdcfg[13], 0xb0);
 304                 break;
 305         case 0x18:
 306                 /*
 307                  * SD2(A:D) => SLOT4 PCIe1
 308                  * SD2(E:F) => SLOT5 Aurora
 309                  * SD2(G:H) => SATA1,SATA2
 310                  */
 311                 QIXIS_WRITE(brdcfg[13], 0x78);
 312                 break;
 313         case 0x1f:
 314                 /*
 315                  * SD2(A:D) => SLOT4 PCIe1
 316                  * SD2(E:H) => SLOT5 PCIe2
 317                  */
 318                 QIXIS_WRITE(brdcfg[13], 0xa0);
 319                 break;
 320         case 0x29:
 321         case 0x2d:
 322         case 0x2e:
 323                 /*
 324                  * SD2(A:D) => SLOT4 SRIO2
 325                  * SD2(E:H) => SLOT5 SRIO1
 326                  */
 327                 QIXIS_WRITE(brdcfg[13], 0xa0);
 328                 break;
 329         case 0x36:
 330                 /*
 331                  * SD2(A:D) => SLOT4 SRIO2
 332                  * SD2(E:F) => Aurora
 333                  * SD2(G:H) => SATA1,SATA2
 334                  */
 335                 QIXIS_WRITE(brdcfg[13], 0x78);
 336                 break;
 337         default:
 338                 printf("WARNING: unsupported for SerDes2 Protocol %d\n",
 339                        srds_prtcl_s2);
 340                 return -1;
 341         }
 342 #endif
 343         return 0;
 344 }
 345
 346 int board_early_init_r(void)
 347 {
 348         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 349         int flash_esel = find_tlb_idx((void *)flashbase, 1);
 350
 351         /*
 352          * Remap Boot flash + PROMJET region to caching-inhibited
 353          * so that flash can be erased properly.
 354          */
 355
 356         /* Flush d-cache and invalidate i-cache of any FLASH data */
 357         flush_dcache();
 358         invalidate_icache();
 359
 360         if (flash_esel == -1) {
 361                 /* very unlikely unless something is messed up */
 362                 puts("Error: Could not find TLB for FLASH BASE\n");
 363                 flash_esel = 2; /* give our best effort to continue */
 364         } else {
 365                 /* invalidate existing TLB entry for flash + promjet */
 366                 disable_tlb(flash_esel);
 367         }
 368
 369         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 370                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 371                 0, flash_esel, BOOKE_PAGESZ_256M, 1);
 372
 373         /* Disable remote I2C connection to qixis fpga */
 374         QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
 375
 376         /*
 377          * Adjust core voltage according to voltage ID
 378          * This function changes I2C mux to channel 2.
 379          */
 380         if (adjust_vdd(0))
 381                 printf("Warning: Adjusting core voltage failed.\n");
 382
 383         brd_mux_lane_to_slot();
 384         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 385
 386         return 0;
 387 }
 388
 389 unsigned long get_board_sys_clk(void)
 390 {
 391         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 392 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
 393         /* use accurate clock measurement */
 394         int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
 395         int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
 396         u32 val;
 397
 398         val =  freq * base;
 399         if (val) {
 400                 debug("SYS Clock measurement is: %d\n", val);
 401                 return val;
 402         } else {
 403                 printf("Warning: SYS clock measurement is invalid, ");
 404                 printf("using value from brdcfg1.\n");
 405         }
 406 #endif
 407
 408         switch (sysclk_conf & 0x0F) {
 409         case QIXIS_SYSCLK_83:
 410                 return 83333333;
 411         case QIXIS_SYSCLK_100:
 412                 return 100000000;
 413         case QIXIS_SYSCLK_125:
 414                 return 125000000;
 415         case QIXIS_SYSCLK_133:
 416                 return 133333333;
 417         case QIXIS_SYSCLK_150:
 418                 return 150000000;
 419         case QIXIS_SYSCLK_160:
 420                 return 160000000;
 421         case QIXIS_SYSCLK_166:
 422                 return 166666666;
 423         }
 424         return 66666666;
 425 }
 426
 427 unsigned long get_board_ddr_clk(void)
 428 {
 429         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 430 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
 431         /* use accurate clock measurement */
 432         int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
 433         int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
 434         u32 val;
 435
 436         val =  freq * base;
 437         if (val) {
 438                 debug("DDR Clock measurement is: %d\n", val);
 439                 return val;
 440         } else {
 441                 printf("Warning: DDR clock measurement is invalid, ");
 442                 printf("using value from brdcfg1.\n");
 443         }
 444 #endif
 445
 446         switch ((ddrclk_conf & 0x30) >> 4) {
 447         case QIXIS_DDRCLK_100:
 448                 return 100000000;
 449         case QIXIS_DDRCLK_125:
 450                 return 125000000;
 451         case QIXIS_DDRCLK_133:
 452                 return 133333333;
 453         }
 454         return 66666666;
 455 }
 456
 457 int misc_init_r(void)
 458 {
 459         return 0;
 460 }
 461
 462 int ft_board_setup(void *blob, bd_t *bd)
 463 {
 464         phys_addr_t base;
 465         phys_size_t size;
 466
 467         ft_cpu_setup(blob, bd);
 468
 469         base = env_get_bootm_low();
 470         size = env_get_bootm_size();
 471
 472         fdt_fixup_memory(blob, (u64)base, (u64)size);
 473
 474 #ifdef CONFIG_PCI
 475         pci_of_setup(blob, bd);
 476 #endif
 477
 478         fdt_fixup_liodn(blob);
 479         fsl_fdt_fixup_dr_usb(blob, bd);
 480
 481 #ifdef CONFIG_SYS_DPAA_FMAN
 482         fdt_fixup_fman_ethernet(blob);
 483         fdt_fixup_board_enet(blob);
 484 #endif
 485
 486         return 0;
 487 }