board/freescale/t208xqds/t208xqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2009-2013 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <command.h>
   8 #include <env.h>
   9 #include <fdt_support.h>
  10 #include <i2c.h>
  11 #include <init.h>
  12 #include <netdev.h>
  13 #include <linux/compiler.h>
  14 #include <asm/mmu.h>
  15 #include <asm/processor.h>
  16 #include <asm/immap_85xx.h>
  17 #include <asm/fsl_law.h>
  18 #include <asm/fsl_serdes.h>
  19 #include <asm/fsl_liodn.h>
  20 #include <fm_eth.h>
  21
  22 #include "../common/qixis.h"
  23 #include "../common/vsc3316_3308.h"
  24 #include "../common/vid.h"
  25 #include "t208xqds.h"
  26 #include "t208xqds_qixis.h"
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 int checkboard(void)
  31 {
  32         char buf[64];
  33         u8 sw;
  34         struct cpu_type *cpu = gd->arch.cpu;
  35         static const char *freq[4] = {
  36                 "100.00MHZ(from 8T49N222A)", "125.00MHz",
  37                 "156.25MHZ", "100.00MHz"
  38         };
  39
  40         printf("Board: %sQDS, ", cpu->name);
  41         sw = QIXIS_READ(arch);
  42         printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
  43         printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  44
  45 #ifdef CONFIG_SDCARD
  46         puts("SD/MMC\n");
  47 #elif CONFIG_SPIFLASH
  48         puts("SPI\n");
  49 #else
  50         sw = QIXIS_READ(brdcfg[0]);
  51         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  52
  53         if (sw < 0x8)
  54                 printf("vBank%d\n", sw);
  55         else if (sw == 0x8)
  56                 puts("Promjet\n");
  57         else if (sw == 0x9)
  58                 puts("NAND\n");
  59         else
  60                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  61 #endif
  62
  63         printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
  64                qixis_read_tag(buf), (int)qixis_read_minor());
  65         /* the timestamp string contains "\n" at the end */
  66         printf(" on %s", qixis_read_time(buf));
  67
  68         puts("SERDES Reference Clocks:\n");
  69         sw = QIXIS_READ(brdcfg[2]);
  70         printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
  71                freq[(sw >> 4) & 0x3]);
  72         printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
  73                freq[sw & 0x3]);
  74
  75         return 0;
  76 }
  77
  78 int select_i2c_ch_pca9547(u8 ch)
  79 {
  80         int ret;
  81
  82         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  83         if (ret) {
  84                 puts("PCA: failed to select proper channel\n");
  85                 return ret;
  86         }
  87
  88         return 0;
  89 }
  90
  91 int i2c_multiplexer_select_vid_channel(u8 channel)
  92 {
  93         return select_i2c_ch_pca9547(channel);
  94 }
  95
  96 int brd_mux_lane_to_slot(void)
  97 {
  98         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  99         u32 srds_prtcl_s1;
 100
 101         srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
 102                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 103         srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 104 #if defined(CONFIG_TARGET_T2080QDS)
 105         u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
 106                                 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 107         srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 108 #endif
 109
 110         switch (srds_prtcl_s1) {
 111         case 0:
 112                 /* SerDes1 is not enabled */
 113                 break;
 114 #if defined(CONFIG_TARGET_T2080QDS)
 115         case 0x1b:
 116         case 0x1c:
 117         case 0xa2:
 118                 /* SD1(A:D) => SLOT3 SGMII
 119                  * SD1(G:H) => SLOT1 SGMII
 120                  */
 121                 QIXIS_WRITE(brdcfg[12], 0x1a);
 122                 break;
 123         case 0x94:
 124         case 0x95:
 125                 /* SD1(A:B) => SLOT3 SGMII@1.25bps
 126                  * SD1(C:D) => SFP Module, SGMII@3.125bps
 127                  * SD1(E:H) => SLOT1 SGMII@1.25bps
 128                  */
 129         case 0x96:
 130                 /* SD1(A:B) => SLOT3 SGMII@1.25bps
 131                  * SD1(C)   => SFP Module, SGMII@3.125bps
 132                  * SD1(D)   => SFP Module, SGMII@1.25bps
 133                  * SD1(E:H) => SLOT1 PCIe4 x4
 134                  */
 135                 QIXIS_WRITE(brdcfg[12], 0x3a);
 136                 break;
 137         case 0x50:
 138         case 0x51:
 139                 /* SD1(A:D) => SLOT3 XAUI
 140                  * SD1(E)   => SLOT1 PCIe4
 141                  * SD1(F:H) => SLOT2 SGMII
 142                  */
 143                 QIXIS_WRITE(brdcfg[12], 0x15);
 144                 break;
 145         case 0x66:
 146         case 0x67:
 147                 /* SD1(A:D) => XFI cage
 148                  * SD1(E:H) => SLOT1 PCIe4
 149                  */
 150                 QIXIS_WRITE(brdcfg[12], 0xfe);
 151                 break;
 152         case 0x6a:
 153         case 0x6b:
 154                 /* SD1(A:D) => XFI cage
 155                  * SD1(E)   => SLOT1 PCIe4
 156                  * SD1(F:H) => SLOT2 SGMII
 157                  */
 158                 QIXIS_WRITE(brdcfg[12], 0xf1);
 159                 break;
 160         case 0x6c:
 161         case 0x6d:
 162                 /* SD1(A:B) => XFI cage
 163                  * SD1(C:D) => SLOT3 SGMII
 164                  * SD1(E:H) => SLOT1 PCIe4
 165                  */
 166                 QIXIS_WRITE(brdcfg[12], 0xda);
 167                 break;
 168         case 0x6e:
 169                 /* SD1(A:B) => SFP Module, XFI
 170                  * SD1(C:D) => SLOT3 SGMII
 171                  * SD1(E:F) => SLOT1 PCIe4 x2
 172                  * SD1(G:H) => SLOT2 SGMII
 173                  */
 174                 QIXIS_WRITE(brdcfg[12], 0xd9);
 175                 break;
 176         case 0xda:
 177                 /* SD1(A:H) => SLOT3 PCIe3 x8
 178                  */
 179                  QIXIS_WRITE(brdcfg[12], 0x0);
 180                  break;
 181         case 0xc8:
 182                 /* SD1(A)   => SLOT3 PCIe3 x1
 183                  * SD1(B)   => SFP Module, SGMII@1.25bps
 184                  * SD1(C:D) => SFP Module, SGMII@3.125bps
 185                  * SD1(E:F) => SLOT1 PCIe4 x2
 186                  * SD1(G:H) => SLOT2 SGMII
 187                  */
 188                  QIXIS_WRITE(brdcfg[12], 0x79);
 189                  break;
 190         case 0xab:
 191                 /* SD1(A:D) => SLOT3 PCIe3 x4
 192                  * SD1(E:H) => SLOT1 PCIe4 x4
 193                  */
 194                  QIXIS_WRITE(brdcfg[12], 0x1a);
 195                  break;
 196 #elif defined(CONFIG_TARGET_T2081QDS)
 197         case 0x50:
 198         case 0x51:
 199                 /* SD1(A:D) => SLOT2 XAUI
 200                  * SD1(E)   => SLOT1 PCIe4 x1
 201                  * SD1(F:H) => SLOT3 SGMII
 202                  */
 203                 QIXIS_WRITE(brdcfg[12], 0x98);
 204                 QIXIS_WRITE(brdcfg[13], 0x70);
 205                 break;
 206         case 0x6a:
 207         case 0x6b:
 208                 /* SD1(A:D) => XFI SFP Module
 209                  * SD1(E)   => SLOT1 PCIe4 x1
 210                  * SD1(F:H) => SLOT3 SGMII
 211                  */
 212                 QIXIS_WRITE(brdcfg[12], 0x80);
 213                 QIXIS_WRITE(brdcfg[13], 0x70);
 214                 break;
 215         case 0x6c:
 216         case 0x6d:
 217                 /* SD1(A:B) => XFI SFP Module
 218                  * SD1(C:D) => SLOT2 SGMII
 219                  * SD1(E:H) => SLOT1 PCIe4 x4
 220                  */
 221                 QIXIS_WRITE(brdcfg[12], 0xe8);
 222                 QIXIS_WRITE(brdcfg[13], 0x0);
 223                 break;
 224         case 0xaa:
 225         case 0xab:
 226                 /* SD1(A:D) => SLOT2 PCIe3 x4
 227                  * SD1(F:H) => SLOT1 SGMI4 x4
 228                  */
 229                 QIXIS_WRITE(brdcfg[12], 0xf8);
 230                 QIXIS_WRITE(brdcfg[13], 0x0);
 231                 break;
 232         case 0xca:
 233         case 0xcb:
 234                 /* SD1(A)   => SLOT2 PCIe3 x1
 235                  * SD1(B)   => SLOT7 SGMII
 236                  * SD1(C)   => SLOT6 SGMII
 237                  * SD1(D)   => SLOT5 SGMII
 238                  * SD1(E)   => SLOT1 PCIe4 x1
 239                  * SD1(F:H) => SLOT3 SGMII
 240                  */
 241                 QIXIS_WRITE(brdcfg[12], 0x80);
 242                 QIXIS_WRITE(brdcfg[13], 0x70);
 243                 break;
 244         case 0xde:
 245         case 0xdf:
 246                 /* SD1(A:D) => SLOT2 PCIe3 x4
 247                  * SD1(E)   => SLOT1 PCIe4 x1
 248                  * SD1(F)   => SLOT4 PCIe1 x1
 249                  * SD1(G)   => SLOT3 PCIe2 x1
 250                  * SD1(H)   => SLOT7 SGMII
 251                  */
 252                 QIXIS_WRITE(brdcfg[12], 0x98);
 253                 QIXIS_WRITE(brdcfg[13], 0x25);
 254                 break;
 255         case 0xf2:
 256                 /* SD1(A)   => SLOT2 PCIe3 x1
 257                  * SD1(B:D) => SLOT7 SGMII
 258                  * SD1(E)   => SLOT1 PCIe4 x1
 259                  * SD1(F)   => SLOT4 PCIe1 x1
 260                  * SD1(G)   => SLOT3 PCIe2 x1
 261                  * SD1(H)   => SLOT7 SGMII
 262                  */
 263                 QIXIS_WRITE(brdcfg[12], 0x81);
 264                 QIXIS_WRITE(brdcfg[13], 0xa5);
 265                 break;
 266 #endif
 267         default:
 268                 printf("WARNING: unsupported for SerDes1 Protocol %d\n",
 269                        srds_prtcl_s1);
 270                 return -1;
 271         }
 272
 273 #ifdef CONFIG_TARGET_T2080QDS
 274         switch (srds_prtcl_s2) {
 275         case 0:
 276                 /* SerDes2 is not enabled */
 277                 break;
 278         case 0x01:
 279         case 0x02:
 280                 /* SD2(A:H) => SLOT4 PCIe1 */
 281                 QIXIS_WRITE(brdcfg[13], 0x10);
 282                 break;
 283         case 0x15:
 284         case 0x16:
 285                 /*
 286                  * SD2(A:D) => SLOT4 PCIe1
 287                  * SD2(E:F) => SLOT5 PCIe2
 288                  * SD2(G:H) => SATA1,SATA2
 289                  */
 290                 QIXIS_WRITE(brdcfg[13], 0xb0);
 291                 break;
 292         case 0x18:
 293                 /*
 294                  * SD2(A:D) => SLOT4 PCIe1
 295                  * SD2(E:F) => SLOT5 Aurora
 296                  * SD2(G:H) => SATA1,SATA2
 297                  */
 298                 QIXIS_WRITE(brdcfg[13], 0x78);
 299                 break;
 300         case 0x1f:
 301                 /*
 302                  * SD2(A:D) => SLOT4 PCIe1
 303                  * SD2(E:H) => SLOT5 PCIe2
 304                  */
 305                 QIXIS_WRITE(brdcfg[13], 0xa0);
 306                 break;
 307         case 0x29:
 308         case 0x2d:
 309         case 0x2e:
 310                 /*
 311                  * SD2(A:D) => SLOT4 SRIO2
 312                  * SD2(E:H) => SLOT5 SRIO1
 313                  */
 314                 QIXIS_WRITE(brdcfg[13], 0xa0);
 315                 break;
 316         case 0x36:
 317                 /*
 318                  * SD2(A:D) => SLOT4 SRIO2
 319                  * SD2(E:F) => Aurora
 320                  * SD2(G:H) => SATA1,SATA2
 321                  */
 322                 QIXIS_WRITE(brdcfg[13], 0x78);
 323                 break;
 324         default:
 325                 printf("WARNING: unsupported for SerDes2 Protocol %d\n",
 326                        srds_prtcl_s2);
 327                 return -1;
 328         }
 329 #endif
 330         return 0;
 331 }
 332
 333 int board_early_init_r(void)
 334 {
 335         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 336         int flash_esel = find_tlb_idx((void *)flashbase, 1);
 337
 338         /*
 339          * Remap Boot flash + PROMJET region to caching-inhibited
 340          * so that flash can be erased properly.
 341          */
 342
 343         /* Flush d-cache and invalidate i-cache of any FLASH data */
 344         flush_dcache();
 345         invalidate_icache();
 346
 347         if (flash_esel == -1) {
 348                 /* very unlikely unless something is messed up */
 349                 puts("Error: Could not find TLB for FLASH BASE\n");
 350                 flash_esel = 2; /* give our best effort to continue */
 351         } else {
 352                 /* invalidate existing TLB entry for flash + promjet */
 353                 disable_tlb(flash_esel);
 354         }
 355
 356         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 357                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 358                 0, flash_esel, BOOKE_PAGESZ_256M, 1);
 359
 360         /* Disable remote I2C connection to qixis fpga */
 361         QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
 362
 363         /*
 364          * Adjust core voltage according to voltage ID
 365          * This function changes I2C mux to channel 2.
 366          */
 367         if (adjust_vdd(0))
 368                 printf("Warning: Adjusting core voltage failed.\n");
 369
 370         brd_mux_lane_to_slot();
 371         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 372
 373         return 0;
 374 }
 375
 376 unsigned long get_board_sys_clk(void)
 377 {
 378         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 379 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
 380         /* use accurate clock measurement */
 381         int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
 382         int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
 383         u32 val;
 384
 385         val =  freq * base;
 386         if (val) {
 387                 debug("SYS Clock measurement is: %d\n", val);
 388                 return val;
 389         } else {
 390                 printf("Warning: SYS clock measurement is invalid, ");
 391                 printf("using value from brdcfg1.\n");
 392         }
 393 #endif
 394
 395         switch (sysclk_conf & 0x0F) {
 396         case QIXIS_SYSCLK_83:
 397                 return 83333333;
 398         case QIXIS_SYSCLK_100:
 399                 return 100000000;
 400         case QIXIS_SYSCLK_125:
 401                 return 125000000;
 402         case QIXIS_SYSCLK_133:
 403                 return 133333333;
 404         case QIXIS_SYSCLK_150:
 405                 return 150000000;
 406         case QIXIS_SYSCLK_160:
 407                 return 160000000;
 408         case QIXIS_SYSCLK_166:
 409                 return 166666666;
 410         }
 411         return 66666666;
 412 }
 413
 414 unsigned long get_board_ddr_clk(void)
 415 {
 416         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 417 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
 418         /* use accurate clock measurement */
 419         int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
 420         int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
 421         u32 val;
 422
 423         val =  freq * base;
 424         if (val) {
 425                 debug("DDR Clock measurement is: %d\n", val);
 426                 return val;
 427         } else {
 428                 printf("Warning: DDR clock measurement is invalid, ");
 429                 printf("using value from brdcfg1.\n");
 430         }
 431 #endif
 432
 433         switch ((ddrclk_conf & 0x30) >> 4) {
 434         case QIXIS_DDRCLK_100:
 435                 return 100000000;
 436         case QIXIS_DDRCLK_125:
 437                 return 125000000;
 438         case QIXIS_DDRCLK_133:
 439                 return 133333333;
 440         }
 441         return 66666666;
 442 }
 443
 444 int misc_init_r(void)
 445 {
 446         return 0;
 447 }
 448
 449 int ft_board_setup(void *blob, bd_t *bd)
 450 {
 451         phys_addr_t base;
 452         phys_size_t size;
 453
 454         ft_cpu_setup(blob, bd);
 455
 456         base = env_get_bootm_low();
 457         size = env_get_bootm_size();
 458
 459         fdt_fixup_memory(blob, (u64)base, (u64)size);
 460
 461 #ifdef CONFIG_PCI
 462         pci_of_setup(blob, bd);
 463 #endif
 464
 465         fdt_fixup_liodn(blob);
 466         fsl_fdt_fixup_dr_usb(blob, bd);
 467
 468 #ifdef CONFIG_SYS_DPAA_FMAN
 469         fdt_fixup_fman_ethernet(blob);
 470         fdt_fixup_board_enet(blob);
 471 #endif
 472
 473         return 0;
 474 }