board/freescale/t208xqds/eth_t208xqds.c

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * Shengzhou Liu <Shengzhou.Liu@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <command.h>
  11 #include <netdev.h>
  12 #include <asm/mmu.h>
  13 #include <asm/processor.h>
  14 #include <asm/immap_85xx.h>
  15 #include <asm/fsl_law.h>
  16 #include <asm/fsl_serdes.h>
  17 #include <asm/fsl_portals.h>
  18 #include <asm/fsl_liodn.h>
  19 #include <malloc.h>
  20 #include <fm_eth.h>
  21 #include <fsl_mdio.h>
  22 #include <miiphy.h>
  23 #include <phy.h>
  24 #include <asm/fsl_dtsec.h>
  25 #include <asm/fsl_serdes.h>
  26 #include <hwconfig.h>
  27 #include "../common/qixis.h"
  28 #include "../common/fman.h"
  29 #include "t208xqds_qixis.h"
  30
  31 #define EMI_NONE        0xFFFFFFFF
  32 #define EMI1_RGMII1     0
  33 #define EMI1_RGMII2     1
  34 #define EMI1_SLOT1      2
  35 #if defined(CONFIG_T2080QDS)
  36 #define EMI1_SLOT2      6
  37 #define EMI1_SLOT3      3
  38 #define EMI1_SLOT4      4
  39 #define EMI1_SLOT5      5
  40 #define EMI2            7
  41 #elif defined(CONFIG_T2081QDS)
  42 #define EMI1_SLOT2      3
  43 #define EMI1_SLOT3      4
  44 #define EMI1_SLOT5      5
  45 #define EMI1_SLOT6      6
  46 #define EMI1_SLOT7      7
  47 #define EMI2            8
  48 #endif
  49
  50 static int mdio_mux[NUM_FM_PORTS];
  51
  52 static const char * const mdio_names[] = {
  53 #if defined(CONFIG_T2080QDS)
  54         "T2080QDS_MDIO_RGMII1",
  55         "T2080QDS_MDIO_RGMII2",
  56         "T2080QDS_MDIO_SLOT1",
  57         "T2080QDS_MDIO_SLOT3",
  58         "T2080QDS_MDIO_SLOT4",
  59         "T2080QDS_MDIO_SLOT5",
  60         "T2080QDS_MDIO_SLOT2",
  61         "T2080QDS_MDIO_10GC",
  62 #elif defined(CONFIG_T2081QDS)
  63         "T2081QDS_MDIO_RGMII1",
  64         "T2081QDS_MDIO_RGMII2",
  65         "T2081QDS_MDIO_SLOT1",
  66         "T2081QDS_MDIO_SLOT2",
  67         "T2081QDS_MDIO_SLOT3",
  68         "T2081QDS_MDIO_SLOT5",
  69         "T2081QDS_MDIO_SLOT6",
  70         "T2081QDS_MDIO_SLOT7",
  71         "T2081QDS_MDIO_10GC",
  72 #endif
  73 };
  74
  75 /* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
  76 #if defined(CONFIG_T2080QDS)
  77 static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
  78 #elif defined(CONFIG_T2081QDS)
  79 static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
  80 #endif
  81
  82 static const char *t208xqds_mdio_name_for_muxval(u8 muxval)
  83 {
  84         return mdio_names[muxval];
  85 }
  86
  87 struct mii_dev *mii_dev_for_muxval(u8 muxval)
  88 {
  89         struct mii_dev *bus;
  90         const char *name = t208xqds_mdio_name_for_muxval(muxval);
  91
  92         if (!name) {
  93                 printf("No bus for muxval %x\n", muxval);
  94                 return NULL;
  95         }
  96
  97         bus = miiphy_get_dev_by_name(name);
  98
  99         if (!bus) {
 100                 printf("No bus by name %s\n", name);
 101                 return NULL;
 102         }
 103
 104         return bus;
 105 }
 106
 107 struct t208xqds_mdio {
 108         u8 muxval;
 109         struct mii_dev *realbus;
 110 };
 111
 112 static void t208xqds_mux_mdio(u8 muxval)
 113 {
 114         u8 brdcfg4;
 115         if (muxval < 8) {
 116                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 117                 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
 118                 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
 119                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 120         }
 121 }
 122
 123 static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad,
 124                                 int regnum)
 125 {
 126         struct t208xqds_mdio *priv = bus->priv;
 127
 128         t208xqds_mux_mdio(priv->muxval);
 129
 130         return priv->realbus->read(priv->realbus, addr, devad, regnum);
 131 }
 132
 133 static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad,
 134                                 int regnum, u16 value)
 135 {
 136         struct t208xqds_mdio *priv = bus->priv;
 137
 138         t208xqds_mux_mdio(priv->muxval);
 139
 140         return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
 141 }
 142
 143 static int t208xqds_mdio_reset(struct mii_dev *bus)
 144 {
 145         struct t208xqds_mdio *priv = bus->priv;
 146
 147         return priv->realbus->reset(priv->realbus);
 148 }
 149
 150 static int t208xqds_mdio_init(char *realbusname, u8 muxval)
 151 {
 152         struct t208xqds_mdio *pmdio;
 153         struct mii_dev *bus = mdio_alloc();
 154
 155         if (!bus) {
 156                 printf("Failed to allocate t208xqds MDIO bus\n");
 157                 return -1;
 158         }
 159
 160         pmdio = malloc(sizeof(*pmdio));
 161         if (!pmdio) {
 162                 printf("Failed to allocate t208xqds private data\n");
 163                 free(bus);
 164                 return -1;
 165         }
 166
 167         bus->read = t208xqds_mdio_read;
 168         bus->write = t208xqds_mdio_write;
 169         bus->reset = t208xqds_mdio_reset;
 170         sprintf(bus->name, t208xqds_mdio_name_for_muxval(muxval));
 171
 172         pmdio->realbus = miiphy_get_dev_by_name(realbusname);
 173
 174         if (!pmdio->realbus) {
 175                 printf("No bus with name %s\n", realbusname);
 176                 free(bus);
 177                 free(pmdio);
 178                 return -1;
 179         }
 180
 181         pmdio->muxval = muxval;
 182         bus->priv = pmdio;
 183         return mdio_register(bus);
 184 }
 185
 186 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 187                                 enum fm_port port, int offset)
 188 {
 189         int phy;
 190         char alias[20];
 191         char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"};
 192         char buf[32] = "serdes-1,";
 193         struct fixed_link f_link;
 194         int media_type = 0;
 195         int off;
 196
 197         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 198         u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
 199                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 200
 201         srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 202
 203         if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
 204                 phy = fm_info_get_phy_address(port);
 205                 switch (port) {
 206 #if defined(CONFIG_T2080QDS)
 207                 case FM1_DTSEC1:
 208                 case FM1_DTSEC2:
 209                 case FM1_DTSEC9:
 210                 case FM1_DTSEC10:
 211                         if (mdio_mux[port] == EMI1_SLOT2) {
 212                                 sprintf(alias, "phy_sgmii_s2_%x", phy);
 213                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 214                                 fdt_status_okay_by_alias(fdt, "emi1_slot2");
 215                         } else if (mdio_mux[port] == EMI1_SLOT3) {
 216                                 sprintf(alias, "phy_sgmii_s3_%x", phy);
 217                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 218                                 fdt_status_okay_by_alias(fdt, "emi1_slot3");
 219                         }
 220                         break;
 221                 case FM1_DTSEC5:
 222                 case FM1_DTSEC6:
 223                         if (mdio_mux[port] == EMI1_SLOT1) {
 224                                 sprintf(alias, "phy_sgmii_s1_%x", phy);
 225                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 226                                 fdt_status_okay_by_alias(fdt, "emi1_slot1");
 227                         } else if (mdio_mux[port] == EMI1_SLOT2) {
 228                                 sprintf(alias, "phy_sgmii_s2_%x", phy);
 229                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 230                                 fdt_status_okay_by_alias(fdt, "emi1_slot2");
 231                         }
 232                         break;
 233 #elif defined(CONFIG_T2081QDS)
 234                 case FM1_DTSEC1:
 235                 case FM1_DTSEC2:
 236                 case FM1_DTSEC5:
 237                 case FM1_DTSEC6:
 238                 case FM1_DTSEC9:
 239                 case FM1_DTSEC10:
 240                         if (mdio_mux[port] == EMI1_SLOT2) {
 241                                 sprintf(alias, "phy_sgmii_s2_%x", phy);
 242                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 243                                 fdt_status_okay_by_alias(fdt, "emi1_slot2");
 244                         } else if (mdio_mux[port] == EMI1_SLOT3) {
 245                                 sprintf(alias, "phy_sgmii_s3_%x", phy);
 246                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 247                                 fdt_status_okay_by_alias(fdt, "emi1_slot3");
 248                         } else if (mdio_mux[port] == EMI1_SLOT5) {
 249                                 sprintf(alias, "phy_sgmii_s5_%x", phy);
 250                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 251                                 fdt_status_okay_by_alias(fdt, "emi1_slot5");
 252                         } else if (mdio_mux[port] == EMI1_SLOT6) {
 253                                 sprintf(alias, "phy_sgmii_s6_%x", phy);
 254                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 255                                 fdt_status_okay_by_alias(fdt, "emi1_slot6");
 256                         } else if (mdio_mux[port] == EMI1_SLOT7) {
 257                                 sprintf(alias, "phy_sgmii_s7_%x", phy);
 258                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 259                                 fdt_status_okay_by_alias(fdt, "emi1_slot7");
 260                         }
 261                         break;
 262 #endif
 263                 default:
 264                         break;
 265                 }
 266
 267         } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
 268                 switch (srds_s1) {
 269                 case 0x66: /* XFI interface */
 270                 case 0x6b:
 271                 case 0x6c:
 272                 case 0x6d:
 273                 case 0x71:
 274                         /*
 275                         * if the 10G is XFI, check hwconfig to see what is the
 276                         * media type, there are two types, fiber or copper,
 277                         * fix the dtb accordingly.
 278                         */
 279                         switch (port) {
 280                         case FM1_10GEC1:
 281                         if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
 282                                 /* it's MAC9 */
 283                                 media_type = 1;
 284                                 fdt_set_phy_handle(fdt, compat, addr,
 285                                                 "phy_xfi9");
 286                                 fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9");
 287                                 sprintf(buf, "%s%s%s", buf, "lane-a,",
 288                                                 (char *)lane_mode[1]);
 289                         }
 290                                 break;
 291                         case FM1_10GEC2:
 292                         if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
 293                                 /* it's MAC10 */
 294                                 media_type = 1;
 295                                 fdt_set_phy_handle(fdt, compat, addr,
 296                                                 "phy_xfi10");
 297                                 fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10");
 298                                 sprintf(buf, "%s%s%s", buf, "lane-b,",
 299                                                 (char *)lane_mode[1]);
 300                         }
 301                                 break;
 302                         case FM1_10GEC3:
 303                         if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) {
 304                                 /* it's MAC1 */
 305                                 media_type = 1;
 306                                 fdt_set_phy_handle(fdt, compat, addr,
 307                                                 "phy_xfi1");
 308                                 fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1");
 309                                 sprintf(buf, "%s%s%s", buf, "lane-c,",
 310                                                 (char *)lane_mode[1]);
 311                         }
 312                                 break;
 313                         case FM1_10GEC4:
 314                         if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) {
 315                                 /* it's MAC2 */
 316                                 media_type = 1;
 317                                 fdt_set_phy_handle(fdt, compat, addr,
 318                                                 "phy_xfi2");
 319                                 fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2");
 320                                 sprintf(buf, "%s%s%s", buf, "lane-d,",
 321                                                 (char *)lane_mode[1]);
 322                         }
 323                                 break;
 324                         default:
 325                                 return;
 326                         }
 327
 328                         if (!media_type) {
 329                                 /* fixed-link is used for XFI fiber cable */
 330                                 f_link.phy_id = port;
 331                                 f_link.duplex = 1;
 332                                 f_link.link_speed = 10000;
 333                                 f_link.pause = 0;
 334                                 f_link.asym_pause = 0;
 335                                 fdt_delprop(fdt, offset, "phy-handle");
 336                                 fdt_setprop(fdt, offset, "fixed-link", &f_link,
 337                                         sizeof(f_link));
 338                         } else {
 339                                 /* set property for copper cable */
 340                                 off = fdt_node_offset_by_compat_reg(fdt,
 341                                         "fsl,fman-memac-mdio", addr + 0x1000);
 342                                 fdt_setprop_string(fdt, off,
 343                                         "lane-instance", buf);
 344                         }
 345                         break;
 346                 default:
 347                         break;
 348                 }
 349         }
 350 }
 351
 352 void fdt_fixup_board_enet(void *fdt)
 353 {
 354         return;
 355 }
 356
 357 /*
 358  * This function reads RCW to check if Serdes1{A:H} is configured
 359  * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly
 360  */
 361 static void initialize_lane_to_slot(void)
 362 {
 363         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 364         u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
 365                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 366
 367         srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 368
 369         switch (srds_s1) {
 370 #if defined(CONFIG_T2080QDS)
 371         case 0x51:
 372         case 0x5f:
 373         case 0x65:
 374         case 0x6b:
 375         case 0x71:
 376                 lane_to_slot[5] = 2;
 377                 lane_to_slot[6] = 2;
 378                 lane_to_slot[7] = 2;
 379                 break;
 380         case 0xa6:
 381         case 0x8e:
 382         case 0x8f:
 383         case 0x82:
 384         case 0x83:
 385         case 0xd3:
 386         case 0xd9:
 387         case 0xcb:
 388                 lane_to_slot[6] = 2;
 389                 lane_to_slot[7] = 2;
 390                 break;
 391         case 0xda:
 392                 lane_to_slot[4] = 3;
 393                 lane_to_slot[5] = 3;
 394                 lane_to_slot[6] = 3;
 395                 lane_to_slot[7] = 3;
 396                 break;
 397 #elif defined(CONFIG_T2081QDS)
 398         case 0x6b:
 399                 lane_to_slot[4] = 1;
 400                 lane_to_slot[5] = 3;
 401                 lane_to_slot[6] = 3;
 402                 lane_to_slot[7] = 3;
 403                 break;
 404         case 0xca:
 405         case 0xcb:
 406                 lane_to_slot[1] = 7;
 407                 lane_to_slot[2] = 6;
 408                 lane_to_slot[3] = 5;
 409                 lane_to_slot[5] = 3;
 410                 lane_to_slot[6] = 3;
 411                 lane_to_slot[7] = 3;
 412                 break;
 413         case 0xf2:
 414                 lane_to_slot[1] = 7;
 415                 lane_to_slot[2] = 7;
 416                 lane_to_slot[3] = 7;
 417                 lane_to_slot[5] = 4;
 418                 lane_to_slot[6] = 3;
 419                 lane_to_slot[7] = 7;
 420                 break;
 421 #endif
 422         default:
 423                 break;
 424         }
 425 }
 426
 427 int board_eth_init(bd_t *bis)
 428 {
 429 #if defined(CONFIG_FMAN_ENET)
 430         int i, idx, lane, slot, interface;
 431         struct memac_mdio_info dtsec_mdio_info;
 432         struct memac_mdio_info tgec_mdio_info;
 433         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 434         u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
 435         u32 srds_s1;
 436
 437         srds_s1 = in_be32(&gur->rcwsr[4]) &
 438                                         FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 439         srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 440
 441         initialize_lane_to_slot();
 442
 443         /* Initialize the mdio_mux array so we can recognize empty elements */
 444         for (i = 0; i < NUM_FM_PORTS; i++)
 445                 mdio_mux[i] = EMI_NONE;
 446
 447         dtsec_mdio_info.regs =
 448                 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
 449
 450         dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 451
 452         /* Register the 1G MDIO bus */
 453         fm_memac_mdio_init(bis, &dtsec_mdio_info);
 454
 455         tgec_mdio_info.regs =
 456                 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
 457         tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 458
 459         /* Register the 10G MDIO bus */
 460         fm_memac_mdio_init(bis, &tgec_mdio_info);
 461
 462         /* Register the muxing front-ends to the MDIO buses */
 463         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
 464         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
 465         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
 466         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
 467         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
 468 #if defined(CONFIG_T2080QDS)
 469         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
 470 #endif
 471         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
 472 #if defined(CONFIG_T2081QDS)
 473         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
 474         t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
 475 #endif
 476         t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
 477
 478         /* Set the two on-board RGMII PHY address */
 479         fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
 480         if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
 481                         FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
 482                 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
 483         else
 484                 fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
 485
 486         switch (srds_s1) {
 487         case 0x1b:
 488         case 0x1c:
 489         case 0x95:
 490         case 0xa2:
 491         case 0x94:
 492                 /* T2080QDS: SGMII in Slot3;  T2081QDS: SGMII in Slot2 */
 493                 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
 494                 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
 495                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 496                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 497                 /* T2080QDS: SGMII in Slot2;  T2081QDS: SGMII in Slot1 */
 498                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 499                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
 500                 break;
 501         case 0x50:
 502         case 0x51:
 503         case 0x5e:
 504         case 0x5f:
 505         case 0x64:
 506         case 0x65:
 507                 /* T2080QDS: XAUI/HiGig in Slot3;  T2081QDS: in Slot2 */
 508                 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
 509                 /* T2080QDS: SGMII in Slot2;  T2081QDS: in Slot3 */
 510                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 511                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
 512                 break;
 513         case 0x66:
 514         case 0x67:
 515                 /*
 516                  * XFI does not need a PHY to work, but to avoid U-boot use
 517                  * default PHY address which is zero to a MAC when it found
 518                  * a MAC has no PHY address, we give a PHY address to XFI
 519                  * MAC, and should not use a real XAUI PHY address, since
 520                  * MDIO can access it successfully, and then MDIO thinks
 521                  * the XAUI card is used for the XFI MAC, which will cause
 522                  * error.
 523                  */
 524                 fm_info_set_phy_address(FM1_10GEC1, 4);
 525                 fm_info_set_phy_address(FM1_10GEC2, 5);
 526                 fm_info_set_phy_address(FM1_10GEC3, 6);
 527                 fm_info_set_phy_address(FM1_10GEC4, 7);
 528                 break;
 529         case 0x6a:
 530         case 0x6b:
 531                 fm_info_set_phy_address(FM1_10GEC1, 4);
 532                 fm_info_set_phy_address(FM1_10GEC2, 5);
 533                 fm_info_set_phy_address(FM1_10GEC3, 6);
 534                 fm_info_set_phy_address(FM1_10GEC4, 7);
 535                 /* T2080QDS: SGMII in Slot2;  T2081QDS: in Slot3 */
 536                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 537                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 538                 break;
 539         case 0x6c:
 540         case 0x6d:
 541                 fm_info_set_phy_address(FM1_10GEC1, 4);
 542                 fm_info_set_phy_address(FM1_10GEC2, 5);
 543                 /* T2080QDS: SGMII in Slot3;  T2081QDS: in Slot2 */
 544                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 545                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 546                 break;
 547         case 0x70:
 548         case 0x71:
 549                 /* SGMII in Slot3 */
 550                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 551                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 552                 /* SGMII in Slot2 */
 553                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 554                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 555                 break;
 556         case 0xa6:
 557         case 0x8e:
 558         case 0x8f:
 559         case 0x82:
 560         case 0x83:
 561                 /* SGMII in Slot3 */
 562                 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
 563                 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
 564                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 565                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 566                 /* SGMII in Slot2 */
 567                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 568                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 569                 break;
 570         case 0xa4:
 571         case 0x96:
 572         case 0x8a:
 573                 /* SGMII in Slot3 */
 574                 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
 575                 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
 576                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 577                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 578                 break;
 579 #if defined(CONFIG_T2080QDS)
 580         case 0xd9:
 581         case 0xd3:
 582         case 0xcb:
 583                 /* SGMII in Slot3 */
 584                 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
 585                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 586                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 587                 /* SGMII in Slot2 */
 588                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 589                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 590                 break;
 591 #elif defined(CONFIG_T2081QDS)
 592         case 0xca:
 593         case 0xcb:
 594                 /* SGMII in Slot3 */
 595                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
 596                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 597                 /* SGMII in Slot5 */
 598                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
 599                 /* SGMII in Slot6 */
 600                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
 601                 /* SGMII in Slot7 */
 602                 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
 603                 break;
 604 #endif
 605         case 0xf2:
 606                 /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
 607                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
 608                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
 609                 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
 610                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
 611                 break;
 612         default:
 613                 break;
 614         }
 615
 616         for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
 617                 idx = i - FM1_DTSEC1;
 618                 interface = fm_info_get_enet_if(i);
 619                 switch (interface) {
 620                 case PHY_INTERFACE_MODE_SGMII:
 621                         lane = serdes_get_first_lane(FSL_SRDS_1,
 622                                         SGMII_FM1_DTSEC1 + idx);
 623                         if (lane < 0)
 624                                 break;
 625                         slot = lane_to_slot[lane];
 626                         debug("FM1@DTSEC%u expects SGMII in slot %u\n",
 627                               idx + 1, slot);
 628                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 629                                 fm_disable_port(i);
 630
 631                         switch (slot) {
 632                         case 1:
 633                                 mdio_mux[i] = EMI1_SLOT1;
 634                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 635                                                  mdio_mux[i]));
 636                                 break;
 637                         case 2:
 638                                 mdio_mux[i] = EMI1_SLOT2;
 639                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 640                                                  mdio_mux[i]));
 641                                 break;
 642                         case 3:
 643                                 mdio_mux[i] = EMI1_SLOT3;
 644                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 645                                                  mdio_mux[i]));
 646                                 break;
 647 #if defined(CONFIG_T2081QDS)
 648                         case 5:
 649                                 mdio_mux[i] = EMI1_SLOT5;
 650                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 651                                                  mdio_mux[i]));
 652                                 break;
 653                         case 6:
 654                                 mdio_mux[i] = EMI1_SLOT6;
 655                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 656                                                  mdio_mux[i]));
 657                                 break;
 658                         case 7:
 659                                 mdio_mux[i] = EMI1_SLOT7;
 660                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 661                                                  mdio_mux[i]));
 662                                 break;
 663 #endif
 664                         }
 665                         break;
 666                 case PHY_INTERFACE_MODE_RGMII:
 667                         if (i == FM1_DTSEC3)
 668                                 mdio_mux[i] = EMI1_RGMII1;
 669                         else if (i == FM1_DTSEC4 || FM1_DTSEC10)
 670                                 mdio_mux[i] = EMI1_RGMII2;
 671                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 672                         break;
 673                 default:
 674                         break;
 675                 }
 676         }
 677
 678         for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
 679                 idx = i - FM1_10GEC1;
 680                 switch (fm_info_get_enet_if(i)) {
 681                 case PHY_INTERFACE_MODE_XGMII:
 682                         if (srds_s1 == 0x51) {
 683                                 lane = serdes_get_first_lane(FSL_SRDS_1,
 684                                                 XAUI_FM1_MAC9 + idx);
 685                         } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
 686                                 lane = serdes_get_first_lane(FSL_SRDS_1,
 687                                                 HIGIG_FM1_MAC9 + idx);
 688                         } else {
 689                                 if (i == FM1_10GEC1 || i == FM1_10GEC2)
 690                                         lane = serdes_get_first_lane(FSL_SRDS_1,
 691                                                 XFI_FM1_MAC9 + idx);
 692                                 else
 693                                         lane = serdes_get_first_lane(FSL_SRDS_1,
 694                                                 XFI_FM1_MAC1 + idx);
 695                         }
 696
 697                         if (lane < 0)
 698                                 break;
 699                         mdio_mux[i] = EMI2;
 700                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 701
 702                         if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
 703                             (srds_s1 == 0x6a) || (srds_s1 == 0x70) ||
 704                             (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
 705                             (srds_s1 == 0x71)) {
 706                                 /* As XFI is in cage intead of a slot, so
 707                                  * ensure doesn't disable the corresponding port
 708                                  */
 709                                 break;
 710                         }
 711
 712                         slot = lane_to_slot[lane];
 713                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 714                                 fm_disable_port(i);
 715                         break;
 716                 default:
 717                         break;
 718                 }
 719         }
 720
 721         cpu_eth_init(bis);
 722 #endif /* CONFIG_FMAN_ENET */
 723
 724         return pci_eth_init(bis);
 725 }