1 The T2080QDS is a high-performance computing evaluation, development and
2 test platform supporting the T2080 QorIQ Power Architecture processor.
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
8 logic and network and peripheral bus interfaces required for networking,
9 telecom/datacom, wireless infrastructure, and mil/aerospace applications.
11 T2080 includes the following functions and features:
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
17 - 16 SerDes lanes up to 10.3125 GHz
18 - 8 Ethernet interfaces, supporting combinations of the following:
19 - Up to four 10 Gbps Ethernet MACs
20 - Up to eight 1 Gbps Ethernet MACs
21 - Up to four 2.5 Gbps Ethernet MACs
22 - High-speed peripheral interfaces
23 - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
24 - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
25 - Additional peripheral interfaces
26 - Two serial ATA (SATA 2.0) controllers
27 - Two high-speed USB 2.0 controllers with integrated PHY
28 - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
29 - Enhanced serial peripheral interface (eSPI)
30 - Four I2C controllers
31 - Four 2-pin UARTs or two 4-pin UARTs
32 - Integrated Flash Controller supporting NAND and NOR flash
33 - Three eight-channel DMA engines
34 - Support for hardware virtualization and partitioning enforcement
35 - QorIQ Platform's Trust Architecture 2.0
37 Differences between T2080 and T2081
38 -----------------------------------
40 1G Ethernet numbers: 8 6
41 10G Ethernet numbers: 4 2
43 Serial RapidIO,RMan: 2 no
46 SoC Package: 896-pins 780-pins
49 T2080QDS feature overview
50 -------------------------
52 - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
54 - Single memory controller capable of supporting DDR3 and DDR3-LV devices
55 - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support
57 - Two 1Gbps RGMII on-board ports
58 - Four 10Gbps XFI on-board cages
59 - 1Gbps/2.5Gbps SGMII Riser card
60 - 10Gbps XAUI Riser card
62 - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
64 - 16 lanes up to 10.3125GHz
65 - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
67 - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
69 - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
71 - Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
73 - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
75 - Two SATA 2.0 ports on-board
77 - Two Serial RapidIO 2.0 ports up to 5 GHz
79 - Supports SD/SDHC/SDXC/eMMC Card
81 - Four I2C controllers.
83 - Dual 4-pins UART serial ports
85 - QIXIS-II FPGA system controll
87 - Support Legacy, COP/JTAG, Aurora, Event and EVT
92 Start Address End Address Description Size
93 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
94 0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
95 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
96 0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
97 0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
98 0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
99 0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
100 0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
101 0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
102 0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
103 0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
104 0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB
105 0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB
106 0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB
107 0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB
108 0x0_0000_0000 0x0_ffff_ffff DDR 4GB
111 128M NOR Flash memory Map
112 -------------------------
113 Start Address End Address Definition Max size
114 0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
115 0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
116 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
117 0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
118 0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
119 0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
120 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
121 0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
122 0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
123 0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
124 0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
125 0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
126 0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
127 0xE8000000 0xE801FFFF RCW (current bank) 128KB
131 Software configurations and board settings
132 ------------------------------------------
134 a. build NOR boot image
135 $ make T2080QDS_config
137 b. program u-boot.bin image to NOR flash
138 => tftp 1000000 u-boot.bin
139 => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
140 set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot
142 Switching between default bank0 and alternate bank4 on NOR flash
143 To change boot source to vbank4:
144 by software: run command 'qixis_reset altbank' in u-boot.
145 by DIP-switch: set SW6[1:4] = '0100'
147 To change boot source to vbank0:
148 by software: run command 'qixis_reset' in u-boot.
149 by DIP-Switch: set SW6[1:4] = '0000'
152 a. build PBL image for NAND boot
153 $ make T2080QDS_NAND_config
155 b. program u-boot-with-spl-pbl.bin to NAND flash
156 => tftp 1000000 u-boot-with-spl-pbl.bin
157 => nand erase 0 $filesize
158 => nand write 1000000 0 $filesize
159 set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot
162 a. build PBL image for SPI boot
163 $ make T2080QDS_SPIFLASH_config
165 b. program u-boot-with-spl-pbl.bin to SPI flash
166 => tftp 1000000 u-boot-with-spl-pbl.bin
169 => sf write 1000000 0 $filesize
170 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
173 a. build PBL image for SD boot
174 $ make T2080QDS_SDCARD_config
176 b. program u-boot-with-spl-pbl.bin to SD/MMC card
177 => tftp 1000000 u-boot-with-spl-pbl.bin
178 => mmc write 1000000 8 0x800
179 => tftp 1000000 fsl_fman_ucode_T2080_xx.bin
180 => mmc write 1000000 0x820 80
181 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
184 2-stage NAND/SPI/SD boot loader
185 -------------------------------
186 PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
187 SPL further initializes DDR using SPD and environment variables
188 and copy u-boot(768 KB) from NAND/SPI/SD device to DDR.
189 Finally SPL transers control to u-boot for futher booting.
191 SPL has following features:
192 - Executes within 256K
193 - No relocation required
195 Run time view of SPL framework
196 -------------------------------------------------
198 -------------------------------------------------
199 |SecureBoot header | 0xFFFC0000 (32KB) |
200 -------------------------------------------------
201 |GD, BD | 0xFFFC8000 (4KB) |
202 -------------------------------------------------
203 |ENV | 0xFFFC9000 (8KB) |
204 -------------------------------------------------
205 |HEAP | 0xFFFCB000 (50KB) |
206 -------------------------------------------------
207 |STACK | 0xFFFD8000 (22KB) |
208 -------------------------------------------------
209 |U-boot SPL | 0xFFFD8000 (160KB) |
210 -------------------------------------------------
212 NAND Flash memory Map on T2080QDS
213 --------------------------------------------------------------
214 Start End Definition Size
215 0x000000 0x0FFFFF u-boot img 1MB (2 blocks)
216 0x100000 0x17FFFF u-boot env 512KB (1 block)
217 0x180000 0x1FFFFF FMAN ucode 512KB (1 block)
220 Micro SD Card memory Map on T2080QDS
221 ----------------------------------------------------
222 Block #blocks Definition Size
223 0x008 2048 u-boot img 1MB
224 0x800 0016 u-boot env 8KB
225 0x820 0128 FMAN ucode 64KB
228 SPI Flash memory Map on T2080QDS
229 ----------------------------------------------------
230 Start End Definition Size
231 0x000000 0x0FFFFF u-boot img 1MB
232 0x100000 0x101FFF u-boot env 8KB
233 0x110000 0x11FFFF FMAN ucode 64KB
236 How to update the ucode of Freescale FMAN
237 -----------------------------------------
238 => tftp 1000000 fsl_fman_ucode_t2080_xx.bin
239 => pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize
242 For more details, please refer to T2080QDS User Guide and access
243 website www.freescale.com and Freescale QorIQ SDK Infocenter document.