board/freescale/t104xrdb/tlb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <asm/mmu.h>
   8
   9 struct fsl_e_tlb_entry tlb_table[] = {
  10         /* TLB 0 - for temp stack in cache */
  11         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  12                       CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  13                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  14                       0, 0, BOOKE_PAGESZ_4K, 0),
  15         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  16                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  17                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  18                       0, 0, BOOKE_PAGESZ_4K, 0),
  19         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  20                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  21                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  22                       0, 0, BOOKE_PAGESZ_4K, 0),
  23         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  24                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  25                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  26                       0, 0, BOOKE_PAGESZ_4K, 0),
  27
  28         /* TLB 1 */
  29         /* *I*** - Covers boot page */
  30 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \
  31         !defined(CONFIG_SECURE_BOOT)
  32         /*
  33          * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
  34          * SRAM is at 0xfffc0000, it covered the 0xfffff000.
  35          */
  36         SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
  37                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  38                       0, 0, BOOKE_PAGESZ_256K, 1),
  39
  40 #elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD)
  41         /*
  42          * *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot
  43          * the physical address of the SRAM is at 0xbffc0000,
  44          * and virtual address is 0xfffc0000
  45          */
  46
  47         SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR,
  48                       CONFIG_SYS_INIT_L3_ADDR,
  49                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  50                       0, 0, BOOKE_PAGESZ_256K, 1),
  51 #else
  52         SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  53                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  54                       0, 0, BOOKE_PAGESZ_4K, 1),
  55 #endif
  56
  57         /* *I*G* - CCSRBAR */
  58         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  59                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  60                       0, 1, BOOKE_PAGESZ_16M, 1),
  61
  62         /* *I*G* - Flash, localbus */
  63         /* This will be changed to *I*G* after relocation to RAM. */
  64         SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  65                       MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  66                       0, 2, BOOKE_PAGESZ_256M, 1),
  67
  68 #ifndef CONFIG_SPL_BUILD
  69         /* *I*G* - PCI */
  70         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  71                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  72                       0, 3, BOOKE_PAGESZ_1G, 1),
  73
  74         /* *I*G* - PCI I/O */
  75         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  76                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  77                       0, 4, BOOKE_PAGESZ_256K, 1),
  78
  79         /* Bman/Qman */
  80 #ifdef CONFIG_SYS_BMAN_MEM_PHYS
  81         SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
  82                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  83                       0, 5, BOOKE_PAGESZ_16M, 1),
  84         SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
  85                       CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
  86                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  87                       0, 6, BOOKE_PAGESZ_16M, 1),
  88 #endif
  89 #ifdef CONFIG_SYS_QMAN_MEM_PHYS
  90         SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
  91                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  92                       0, 7, BOOKE_PAGESZ_16M, 1),
  93         SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
  94                       CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
  95                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  96                       0, 8, BOOKE_PAGESZ_16M, 1),
  97 #endif
  98 #endif
  99 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 100         SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
 101                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 102                       0, 9, BOOKE_PAGESZ_4M, 1),
 103 #endif
 104 #ifdef CONFIG_SYS_NAND_BASE
 105         /*
 106          * *I*G - NAND
 107          * entry 14 and 15 has been used hard coded, they will be disabled
 108          * in cpu_init_f, so we use entry 16 for nand.
 109          */
 110         SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 111                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 112                       0, 10, BOOKE_PAGESZ_64K, 1),
 113 #endif
 114 #ifdef CONFIG_SYS_CPLD_BASE
 115         SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
 116                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 117                       0, 11, BOOKE_PAGESZ_256K, 1),
 118 #endif
 119
 120 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
 121         SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 122                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 123                       0, 12, BOOKE_PAGESZ_1G, 1),
 124         SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 125                       CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 126                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 127                       0, 13, BOOKE_PAGESZ_1G, 1)
 128 #endif
 129 };
 130
 131 int num_tlb_entries = ARRAY_SIZE(tlb_table);