board/freescale/t104xrdb/t104xrdb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <command.h>
   8 #include <env.h>
   9 #include <fdt_support.h>
  10 #include <hwconfig.h>
  11 #include <image.h>
  12 #include <init.h>
  13 #include <netdev.h>
  14 #include <linux/compiler.h>
  15 #include <asm/mmu.h>
  16 #include <asm/processor.h>
  17 #include <asm/cache.h>
  18 #include <asm/immap_85xx.h>
  19 #include <asm/fsl_fdt.h>
  20 #include <asm/fsl_law.h>
  21 #include <asm/fsl_serdes.h>
  22 #include <asm/fsl_liodn.h>
  23 #include <fm_eth.h>
  24 #include "../common/sleep.h"
  25 #include "t104xrdb.h"
  26 #include "cpld.h"
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 int checkboard(void)
  31 {
  32         struct cpu_type *cpu = gd->arch.cpu;
  33         u8 sw;
  34
  35 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
  36         printf("Board: %sD4RDB\n", cpu->name);
  37 #else
  38         printf("Board: %sRDB\n", cpu->name);
  39 #endif
  40         printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
  41                CPLD_READ(hw_ver), CPLD_READ(sw_ver));
  42
  43         sw = CPLD_READ(flash_ctl_status);
  44         sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
  45
  46         printf("vBank: %d\n", sw);
  47
  48         return 0;
  49 }
  50
  51 int board_early_init_f(void)
  52 {
  53 #if defined(CONFIG_DEEP_SLEEP)
  54         if (is_warm_boot())
  55                 fsl_dp_disable_console();
  56 #endif
  57
  58         return 0;
  59 }
  60
  61 int board_early_init_r(void)
  62 {
  63 #ifdef CONFIG_SYS_FLASH_BASE
  64         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  65         int flash_esel = find_tlb_idx((void *)flashbase, 1);
  66
  67         /*
  68          * Remap Boot flash region to caching-inhibited
  69          * so that flash can be erased properly.
  70          */
  71
  72         /* Flush d-cache and invalidate i-cache of any FLASH data */
  73         flush_dcache();
  74         invalidate_icache();
  75
  76         if (flash_esel == -1) {
  77                 /* very unlikely unless something is messed up */
  78                 puts("Error: Could not find TLB for FLASH BASE\n");
  79                 flash_esel = 2; /* give our best effort to continue */
  80         } else {
  81                 /* invalidate existing TLB entry for flash */
  82                 disable_tlb(flash_esel);
  83         }
  84
  85         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  86                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  87                 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  88 #endif
  89         return 0;
  90 }
  91
  92 int misc_init_r(void)
  93 {
  94         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  95         u32 srds_s1;
  96
  97         srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;
  98
  99         printf("SERDES Reference : 0x%X\n", srds_s1);
 100
 101         /* select SGMII*/
 102         if (srds_s1 == 0x86)
 103                 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
 104                                          MISC_CTL_SG_SEL);
 105
 106         /* select SGMII and Aurora*/
 107         if (srds_s1 == 0x8E)
 108                 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
 109                                          MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
 110
 111 #if defined(CONFIG_TARGET_T1040D4RDB)
 112         if (hwconfig("qe-tdm")) {
 113                 CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) |
 114                            MISC_MUX_QE_TDM);
 115                 printf("QECSR : 0x%02x, mux to qe-tdm\n",
 116                        CPLD_READ(sfp_ctl_status));
 117         }
 118         /* Mask all CPLD interrupt sources, except QSGMII interrupts */
 119         if (CPLD_READ(sw_ver) < 0x03) {
 120                 debug("CPLD SW version 0x%02x doesn't support int_mask\n",
 121                       CPLD_READ(sw_ver));
 122         } else {
 123                 CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL &
 124                            ~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2));
 125         }
 126 #endif
 127
 128         return 0;
 129 }
 130
 131 int ft_board_setup(void *blob, bd_t *bd)
 132 {
 133         phys_addr_t base;
 134         phys_size_t size;
 135
 136         ft_cpu_setup(blob, bd);
 137
 138         base = env_get_bootm_low();
 139         size = env_get_bootm_size();
 140
 141         fdt_fixup_memory(blob, (u64)base, (u64)size);
 142
 143 #ifdef CONFIG_PCI
 144         pci_of_setup(blob, bd);
 145 #endif
 146
 147         fdt_fixup_liodn(blob);
 148
 149 #ifdef CONFIG_HAS_FSL_DR_USB
 150         fsl_fdt_fixup_dr_usb(blob, bd);
 151 #endif
 152
 153 #ifdef CONFIG_SYS_DPAA_FMAN
 154         fdt_fixup_fman_ethernet(blob);
 155 #endif
 156
 157         if (hwconfig("qe-tdm"))
 158                 fdt_del_diu(blob);
 159         return 0;
 160 }