board/freescale/t104xrdb/t104xrdb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <command.h>
   8 #include <env.h>
   9 #include <fdt_support.h>
  10 #include <hwconfig.h>
  11 #include <image.h>
  12 #include <init.h>
  13 #include <log.h>
  14 #include <netdev.h>
  15 #include <linux/compiler.h>
  16 #include <asm/mmu.h>
  17 #include <asm/processor.h>
  18 #include <asm/cache.h>
  19 #include <asm/immap_85xx.h>
  20 #include <asm/fsl_fdt.h>
  21 #include <asm/fsl_law.h>
  22 #include <asm/fsl_serdes.h>
  23 #include <asm/fsl_liodn.h>
  24 #include <fm_eth.h>
  25 #include "../common/sleep.h"
  26 #include "t104xrdb.h"
  27 #include "cpld.h"
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 int checkboard(void)
  32 {
  33         struct cpu_type *cpu = gd->arch.cpu;
  34         u8 sw;
  35
  36 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
  37         printf("Board: %sD4RDB\n", cpu->name);
  38 #else
  39         printf("Board: %sRDB\n", cpu->name);
  40 #endif
  41         printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
  42                CPLD_READ(hw_ver), CPLD_READ(sw_ver));
  43
  44         sw = CPLD_READ(flash_ctl_status);
  45         sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
  46
  47         printf("vBank: %d\n", sw);
  48
  49         return 0;
  50 }
  51
  52 int board_early_init_f(void)
  53 {
  54 #if defined(CONFIG_DEEP_SLEEP)
  55         if (is_warm_boot())
  56                 fsl_dp_disable_console();
  57 #endif
  58
  59         return 0;
  60 }
  61
  62 int board_early_init_r(void)
  63 {
  64 #ifdef CONFIG_SYS_FLASH_BASE
  65         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  66         int flash_esel = find_tlb_idx((void *)flashbase, 1);
  67
  68         /*
  69          * Remap Boot flash region to caching-inhibited
  70          * so that flash can be erased properly.
  71          */
  72
  73         /* Flush d-cache and invalidate i-cache of any FLASH data */
  74         flush_dcache();
  75         invalidate_icache();
  76
  77         if (flash_esel == -1) {
  78                 /* very unlikely unless something is messed up */
  79                 puts("Error: Could not find TLB for FLASH BASE\n");
  80                 flash_esel = 2; /* give our best effort to continue */
  81         } else {
  82                 /* invalidate existing TLB entry for flash */
  83                 disable_tlb(flash_esel);
  84         }
  85
  86         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  87                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  88                 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  89 #endif
  90         return 0;
  91 }
  92
  93 int misc_init_r(void)
  94 {
  95         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  96         u32 srds_s1;
  97
  98         srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;
  99
 100         printf("SERDES Reference : 0x%X\n", srds_s1);
 101
 102         /* select SGMII*/
 103         if (srds_s1 == 0x86)
 104                 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
 105                                          MISC_CTL_SG_SEL);
 106
 107         /* select SGMII and Aurora*/
 108         if (srds_s1 == 0x8E)
 109                 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
 110                                          MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
 111
 112 #if defined(CONFIG_TARGET_T1040D4RDB)
 113         if (hwconfig("qe-tdm")) {
 114                 CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) |
 115                            MISC_MUX_QE_TDM);
 116                 printf("QECSR : 0x%02x, mux to qe-tdm\n",
 117                        CPLD_READ(sfp_ctl_status));
 118         }
 119         /* Mask all CPLD interrupt sources, except QSGMII interrupts */
 120         if (CPLD_READ(sw_ver) < 0x03) {
 121                 debug("CPLD SW version 0x%02x doesn't support int_mask\n",
 122                       CPLD_READ(sw_ver));
 123         } else {
 124                 CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL &
 125                            ~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2));
 126         }
 127 #endif
 128
 129         return 0;
 130 }
 131
 132 int ft_board_setup(void *blob, bd_t *bd)
 133 {
 134         phys_addr_t base;
 135         phys_size_t size;
 136
 137         ft_cpu_setup(blob, bd);
 138
 139         base = env_get_bootm_low();
 140         size = env_get_bootm_size();
 141
 142         fdt_fixup_memory(blob, (u64)base, (u64)size);
 143
 144 #ifdef CONFIG_PCI
 145         pci_of_setup(blob, bd);
 146 #endif
 147
 148         fdt_fixup_liodn(blob);
 149
 150 #ifdef CONFIG_HAS_FSL_DR_USB
 151         fsl_fdt_fixup_dr_usb(blob, bd);
 152 #endif
 153
 154 #ifdef CONFIG_SYS_DPAA_FMAN
 155         fdt_fixup_fman_ethernet(blob);
 156 #endif
 157
 158         if (hwconfig("qe-tdm"))
 159                 fdt_del_diu(blob);
 160         return 0;
 161 }