2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <fsl_ddr_sdram.h>
12 #include <fsl_ddr_dimm_params.h>
13 #include <asm/fsl_law.h>
14 #include <asm/mpc85xx_gpio.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
20 unsigned int controller_number,
21 unsigned int dimm_number)
23 const char dimm_model[] = "RAW timing DDR";
25 if ((controller_number == 0) && (dimm_number == 0)) {
26 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
27 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
28 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
34 void fsl_ddr_board_options(memctl_options_t *popts,
36 unsigned int ctrl_num)
38 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
42 printf("Not supported controller number %d\n", ctrl_num);
50 /* Get clk_adjust according to the board ddr
51 * freqency and n_banks specified in board_specific_parameters table.
53 ddr_freq = get_ddr_freq(0) / 1000000;
54 while (pbsp->datarate_mhz_high) {
55 if (pbsp->n_ranks == pdimm->n_ranks &&
56 (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
57 if (ddr_freq <= pbsp->datarate_mhz_high) {
58 popts->clk_adjust = pbsp->clk_adjust;
59 popts->wrlvl_start = pbsp->wrlvl_start;
60 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
61 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
70 printf("Error: board specific timing not found\n");
71 printf("for data rate %lu MT/s\n", ddr_freq);
72 printf("Trying to use the highest speed (%u) parameters\n",
73 pbsp_highest->datarate_mhz_high);
74 popts->clk_adjust = pbsp_highest->clk_adjust;
75 popts->wrlvl_start = pbsp_highest->wrlvl_start;
76 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
77 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
79 panic("DIMM is not supported by this board");
82 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
83 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
84 "wrlvl_ctrl_3 0x%x\n",
85 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
86 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
90 * Factors to consider for half-strength driver enable:
91 * - number of DIMMs installed
93 popts->half_strength_driver_enable = 0;
95 * Write leveling override
97 popts->wrlvl_override = 1;
98 popts->wrlvl_sample = 0xf;
101 * rtt and rtt_wr override
103 popts->rtt_override = 0;
105 /* Enable ZQ calibration */
108 /* DHC_EN =1, ODT = 75 Ohm */
109 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
110 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
113 #if defined(CONFIG_DEEP_SLEEP)
114 void board_mem_sleep_setup(void)
116 void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
118 /* does not provide HW signals for power management */
119 clrbits_8(cpld_base + 0x17, 0x40);
120 /* Disable MCKE isolation */
121 gpio_set_value(2, 0);
126 phys_size_t initdram(int board_type)
128 phys_size_t dram_size;
130 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
131 puts("Initializing....using SPD\n");
133 dram_size = fsl_ddr_sdram();
135 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
136 dram_size *= 0x100000;
139 dram_size = fsl_ddr_sdram_size();
142 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)