1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2013 Freescale Semiconductor, Inc.
10 #include <fdt_support.h>
15 #include <linux/compiler.h>
17 #include <asm/processor.h>
18 #include <asm/cache.h>
19 #include <asm/immap_85xx.h>
20 #include <asm/fsl_law.h>
21 #include <asm/fsl_serdes.h>
22 #include <asm/fsl_liodn.h>
26 #include "../common/sleep.h"
27 #include "../common/qixis.h"
29 #include "t1040qds_qixis.h"
31 DECLARE_GLOBAL_DATA_PTR;
37 struct cpu_type *cpu = gd->arch.cpu;
38 static const char *const freq[] = {"100", "125", "156.25", "161.13",
39 "122.88", "122.88", "122.88"};
42 printf("Board: %sQDS, ", cpu->name);
43 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
44 QIXIS_READ(id), QIXIS_READ(arch));
46 sw = QIXIS_READ(brdcfg[0]);
47 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
50 printf("vBank: %d\n", sw);
58 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
60 printf("FPGA: v%d (%s), build %d",
61 (int)QIXIS_READ(scver), qixis_read_tag(buf),
62 (int)qixis_read_minor());
63 /* the timestamp string contains "\n" at the end */
64 printf(" on %s", qixis_read_time(buf));
67 * Display the actual SERDES reference clocks as configured by the
68 * dip switches on the board. Note that the SWx registers could
69 * technically be set to force the reference clocks to match the
70 * values that the SERDES expects (or vice versa). For now, however,
71 * we just display both values and hope the user notices when they
74 puts("SERDES Reference: ");
75 sw = QIXIS_READ(brdcfg[2]);
76 clock = (sw >> 6) & 3;
77 printf("Clock1=%sMHz ", freq[clock]);
78 clock = (sw >> 4) & 3;
79 printf("Clock2=%sMHz\n", freq[clock]);
84 int select_i2c_ch_pca9547(u8 ch, int bus_num)
91 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
93 printf("%s: Cannot find udev for a bus %d\n", __func__,
98 ret = dm_i2c_write(dev, 0, &ch, 1);
100 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
103 puts("PCA: failed to select proper channel\n");
110 static void qe_board_setup(void)
112 u8 brdcfg15, brdcfg9;
114 if (hwconfig("qe") && hwconfig("tdm")) {
115 brdcfg15 = QIXIS_READ(brdcfg[15]);
117 * TDMRiser uses QE-TDM
118 * Route QE_TDM signals to TDM Riser slot
120 QIXIS_WRITE(brdcfg[15], brdcfg15 | 7);
121 } else if (hwconfig("qe") && hwconfig("uart")) {
122 brdcfg15 = QIXIS_READ(brdcfg[15]);
123 brdcfg9 = QIXIS_READ(brdcfg[9]);
125 * Route QE_TDM signals to UCC
126 * ProfiBus controlled by UCC3
129 QIXIS_WRITE(brdcfg[15], brdcfg15 | 2);
130 QIXIS_WRITE(brdcfg[9], brdcfg9 | 4);
134 int board_early_init_f(void)
136 #if defined(CONFIG_DEEP_SLEEP)
138 fsl_dp_disable_console();
144 int board_early_init_r(void)
146 #ifdef CONFIG_SYS_FLASH_BASE
147 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
148 int flash_esel = find_tlb_idx((void *)flashbase, 1);
151 * Remap Boot flash + PROMJET region to caching-inhibited
152 * so that flash can be erased properly.
155 /* Flush d-cache and invalidate i-cache of any FLASH data */
159 if (flash_esel == -1) {
160 /* very unlikely unless something is messed up */
161 puts("Error: Could not find TLB for FLASH BASE\n");
162 flash_esel = 2; /* give our best effort to continue */
164 /* invalidate existing TLB entry for flash + promjet */
165 disable_tlb(flash_esel);
168 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
169 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
170 0, flash_esel, BOOKE_PAGESZ_256M, 1);
172 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
177 unsigned long get_board_sys_clk(void)
179 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
181 switch (sysclk_conf & 0x0F) {
182 case QIXIS_SYSCLK_64:
184 case QIXIS_SYSCLK_83:
186 case QIXIS_SYSCLK_100:
188 case QIXIS_SYSCLK_125:
190 case QIXIS_SYSCLK_133:
192 case QIXIS_SYSCLK_150:
194 case QIXIS_SYSCLK_160:
196 case QIXIS_SYSCLK_166:
202 unsigned long get_board_ddr_clk(void)
204 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
206 switch ((ddrclk_conf & 0x30) >> 4) {
207 case QIXIS_DDRCLK_100:
209 case QIXIS_DDRCLK_125:
211 case QIXIS_DDRCLK_133:
217 #define NUM_SRDS_BANKS 2
218 int misc_init_r(void)
221 serdes_corenet_t *srds_regs =
222 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
223 u32 actual[NUM_SRDS_BANKS] = { 0 };
226 sw = QIXIS_READ(brdcfg[2]);
227 for (i = 0; i < NUM_SRDS_BANKS; i++) {
228 unsigned int clock = (sw >> (6 - 2 * i)) & 3;
231 actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
234 actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
237 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
243 for (i = 0; i < NUM_SRDS_BANKS; i++) {
244 u32 pllcr0 = srds_regs->bank[i].pllcr0;
245 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
246 if (expected != actual[i]) {
247 printf("expects ref clk%d %sMHz, but actual is %sMHz\n",
248 i + 1, serdes_clock_to_string(expected),
249 serdes_clock_to_string(actual[i]));
258 int ft_board_setup(void *blob, bd_t *bd)
263 ft_cpu_setup(blob, bd);
265 base = env_get_bootm_low();
266 size = env_get_bootm_size();
268 fdt_fixup_memory(blob, (u64)base, (u64)size);
271 pci_of_setup(blob, bd);
274 fdt_fixup_liodn(blob);
276 #ifdef CONFIG_HAS_FSL_DR_USB
277 fsl_fdt_fixup_dr_usb(blob, bd);
280 #ifdef CONFIG_SYS_DPAA_FMAN
281 fdt_fixup_fman_ethernet(blob);
282 fdt_fixup_board_enet(blob);
288 void qixis_dump_switch(void)
292 QIXIS_WRITE(cms[0], 0x00);
293 nr_of_cfgsw = QIXIS_READ(cms[1]);
295 puts("DIP switch settings dump:\n");
296 for (i = 1; i <= nr_of_cfgsw; i++) {
297 QIXIS_WRITE(cms[0], i);
298 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
302 int board_need_mem_reset(void)